Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD•D or a CD ROM•D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator can omit the labor of disconnecting many cables connected to the portreplicator.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD•D or a CD ROM•D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator can omit the labor of disconnecting many cables connected to the portreplicator.

Abstract: A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD•D or a CD ROM•D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator can omit the labor of disconnecting many cables connected to the portreplicator.

Abstract: A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD·D or a CD ROM·D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator can omit the labor of disconnecting many cables connected to the portreplicator.

Abstract: A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD•D or a CD-ROM•D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator or removal of the main body and the file basestation can omit the labor of disconnecting many cables connected to the portreplicator.

Abstract: A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD·D or a CD-ROM·D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator or removal of the main body and the file basestation can omit the labor of disconnecting many cables connected to the portreplicator.

Abstract: An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: An information processor including a keyboard, a main body and a display device. The keyboard is provided with plural infrared-ray emission elements which are located at different positions so as to face in different directions, and an identifying code setting switch for setting the identification code of the keyboard into an infrared-ray signal transmitted from each infrared-ray emission element. The main body includes plural infrared-ray receiving elements which are located at different positions so as to face in different directions, an identifying code setting switch for setting the identification code of the keyboard, and a keyboard controller for judging whether the same identification code as set by the identification code setting switch is contained in the infrared-ray signal which is received by any one of the infrared-ray receiving elements.

Abstract: A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD•D or a CD-ROM•D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator or removal of the main body and the file basestation can omit the labor of disconnecting many cables connected to the portreplicator.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before.

Abstract: A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD·D or a CD-ROM·D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator or removal of the main body and the file basestation can omit the labor of disconnecting many cables connected to the portreplicator.

Abstract: An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before.