Patents by Inventor Hideaki Harakawa
Hideaki Harakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10957702Abstract: According to an embodiment, a semiconductor memory device includes: a first stacked body including a first semiconductor layer, a first memory film, a second semiconductor layer and a first insulating layer; a joining member provided on the first semiconductor layer, the second semiconductor layer, and the first insulating layer; a first layer provided above the joining member and covering the first semiconductor layer and the first memory film; a second layer provided above the joining member, located away from the first layer as viewed in a second direction perpendicular to the first direction, and covering the second semiconductor layer and the second memory film; a second stacked body including a third semiconductor layer, a fourth semiconductor layer, a fourth memory film and a second insulating layer.Type: GrantFiled: March 7, 2019Date of Patent: March 23, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Atsushi Oga, Hideaki Harakawa, Satoshi Nagashima, Natsuki Fukuda
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Patent number: 10833096Abstract: According to one embodiment, a semiconductor device includes: a first pillar penetrating a first stack and including a first insulator, a first portion of a first semiconductor provided on an upper and an outer side surface of the first insulator, a second insulator provided on an outer side surface of the first portion, and a second portion being provided above the first stack, being coupled to an upper surface of the first portion, and including a lower surface greater than the upper surface of the first portion; an oxide film provided on a side surface of the second portion; and a second pillar penetrating a second stack and including a second semiconductor electrically coupled to the first semiconductor, and a third insulator on an outer side surface of the second semiconductor.Type: GrantFiled: August 31, 2018Date of Patent: November 10, 2020Assignee: Toshiba Memory CorporationInventors: Ryo Tanaka, Hiroyuki Yamasaki, Hideaki Harakawa
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Patent number: 10734406Abstract: According to one embodiment, a semiconductor memory device includes first conductive films, a second conductive film, a first pillar including a first semiconductor film and a first insulator, a second semiconductor film, and a second pillar including a second insulator and a third conductive film. The first conductive films are stacked with respective insulator layers interposed therebetween. The second conductive film is provided above the first conductive films with an insulator layer interposed therebetween. The first semiconductor film penetrate the first conductive films in a stacking direction of the first conductive films. The first insulator is provided on a side surface of the first semiconductor film.Type: GrantFiled: February 25, 2019Date of Patent: August 4, 2020Assignee: Toshiba Memory CorporationInventors: Hiroyuki Yamasaki, Hideaki Harakawa
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Publication number: 20200075615Abstract: According to an embodiment, a semiconductor memory device includes: a first stacked body including a first semiconductor layer, a first memory film, a second semiconductor layer and a first insulating layer; a joining member provided on the first semiconductor layer, the second semiconductor layer, and the first insulating layer; a first layer provided above the joining member and covering the first semiconductor layer and the first memory film; a second layer provided above the joining member, located away from the first layer as viewed in a second direction perpendicular to the first direction, and covering the second semiconductor layer and the second memory film; a second stacked body including a third semiconductor layer, a fourth semiconductor layer, a fourth memory film and a second insulating layer.Type: ApplicationFiled: March 7, 2019Publication date: March 5, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Atsushi OGA, Hideaki HARAKAWA, Satoshi NAGASHIMA, Natsuki FUKUDA
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Publication number: 20200066749Abstract: According to one embodiment, a semiconductor memory device includes first conductive films, a second conductive film, a first pillar including a first semiconductor film and a first insulator, a second semiconductor film, and a second pillar including a second insulator and a third conductive film. The first conductive films are stacked with respective insulator layers interposed therebetween. The second conductive film is provided above the first conductive films with an insulator layer interposed therebetween. The first semiconductor film penetrate the first conductive films in a stacking direction of the first conductive films. The first insulator is provided on a side surface of the first semiconductor film.Type: ApplicationFiled: February 25, 2019Publication date: February 27, 2020Applicant: Toshiba Memory CorporationInventors: Hiroyuki YAMASAKI, Hideaki HARAKAWA
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Publication number: 20190287994Abstract: According to one embodiment, a semiconductor device includes: a first pillar penetrating a first stack and including a first insulator, a first portion of a first semiconductor provided on an upper and an outer side surface of the first insulator, a second insulator provided on an outer side surface of the first portion, and a second portion being provided above the first stack, being coupled to an upper surface of the first portion, and including a lower surface greater than the upper surface of the first portion; an oxide film provided on a side surface of the second portion; and a second pillar penetrating a second stack and including a second semiconductor electrically coupled to the first semiconductor, and a third insulator on an outer side surface of the second semiconductor.Type: ApplicationFiled: August 31, 2018Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventors: Ryo TANAKA, Hiroyuki Yamasaki, Hideaki Harakawa
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Publication number: 20160322379Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, a charge accumulation layer, and a contact. The plurality of control gate electrodes are stacked on a substrate. The semiconductor layer has one end thereof connected to the substrate, has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. The contact has its lower end connected to the substrate, and has its lower end and its upper end configured from a metal silicide.Type: ApplicationFiled: September 9, 2015Publication date: November 3, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Takao OOMORI, Takanobu ITOH, Hisataka MEGURO, Hideaki HARAKAWA
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Patent number: 9035402Abstract: According to one embodiment, a semiconductor memory device comprises a cell transistor includes a first gate electrode buried in a semiconductor substrate and a first diffusion layer and a second diffusion layer formed to sandwich the first gate electrode, a first lower electrode formed on the first diffusion layer, a magnetoresistive element formed on the first lower electrode to store data according to a change in a magnetization state and connected to a bit line located above, a second lower electrode formed on the second diffusion layer, and a first contact formed on the second lower electrode and connected to a source line located above. A contact area between the second lower electrode and the second diffusion layer is larger than a contact area between the first contact and the second lower electrode.Type: GrantFiled: August 9, 2013Date of Patent: May 19, 2015Inventors: Yoshiaki Asao, Hideaki Harakawa
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Publication number: 20140284533Abstract: According to one embodiment, a semiconductor memory device comprises a cell transistor includes a first gate electrode buried in a semiconductor substrate and a first diffusion layer and a second diffusion layer formed to sandwich the first gate electrode, a first lower electrode formed on the first diffusion layer, a magnetoresistive element formed on the first lower electrode to store data according to a change in a magnetization state and connected to a bit line located above, a second lower electrode formed on the second diffusion layer, and a first contact formed on the second lower electrode and connected to a source line located above. A contact area between the second lower electrode and the second diffusion layer is larger than a contact area between the first contact and the second lower electrode.Type: ApplicationFiled: August 9, 2013Publication date: September 25, 2014Inventors: Yoshiaki ASAO, Hideaki HARAKAWA
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Patent number: 8716818Abstract: According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B4C, Al2O3 and AlN.Type: GrantFiled: March 23, 2012Date of Patent: May 6, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masatoshi Yoshikawa, Satoshi Seto, Hideaki Harakawa, Jyunichi Ozeki, Tatsuya Kishi, Keiji Hosotani
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Publication number: 20130316536Abstract: A semiconductor manufacturing apparatus according to an embodiment includes a stage capable of mounting a semiconductor substrate thereon, a first irradiation part configured to irradiate an etching beam onto the semiconductor substrate from a first direction inclined at an arbitrary angle with respect to a vertical direction to a surface of the semiconductor substrate, and a second irradiation part configured to irradiate an etching beam onto the semiconductor substrate from a second direction inclined at an arbitrary angle with respect to the vertical direction. The first and second irradiation parts simultaneously irradiate the etching beams when processing the semiconductor substrate or a material on the semiconductor substrate.Type: ApplicationFiled: February 28, 2013Publication date: November 28, 2013Inventors: Satoshi SETO, Hideaki HARAKAWA
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Publication number: 20130001652Abstract: According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B4C, Al2O3 and AlN.Type: ApplicationFiled: March 23, 2012Publication date: January 3, 2013Inventors: Masatoshi Yoshikawa, Satoshi Seto, Hideaki Harakawa, Jyunichi Ozeki, Tatsuya Kishi, Keiji Hosotani
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Publication number: 20120248517Abstract: According to one embodiment, a magnetic memory device includes a substrate and a plurality of magneto-resistive effect devices provided on a substrate. Two of the plurality of magneto-resistive effect devices, that are nearest to each other when viewed from above, differ from each other in distance from the substrate.Type: ApplicationFiled: September 22, 2011Publication date: October 4, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hideaki HARAKAWA
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Patent number: 8232197Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.Type: GrantFiled: September 9, 2009Date of Patent: July 31, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko
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Patent number: 8053268Abstract: A semiconductor device has a semiconductor substrate including a light receiving element, a silicon oxide film formed on the semiconductor substrate, a plurality of wiring interlayer films formed on the silicon oxide film, and each including a wiring layer formed as the result of the fact that copper is buried, and a silicon nitride film formed on the wiring interlayer film of the uppermost layer wherein Si—H concentration is smaller than N—H concentration.Type: GrantFiled: October 28, 2008Date of Patent: November 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Mari Otsuka, Hiroyuki Kamijiyo, Hideaki Harakawa
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Publication number: 20110248368Abstract: A semiconductor device has a semiconductor substrate including a light receiving element, a silicon oxide film formed on the semiconductor substrate, a plurality of wiring interlayer films formed on the silicon oxide film, and each including a wiring layer formed as the result of the fact that copper is buried, and a silicon nitride film formed on the wiring interlayer film of the uppermost layer wherein Si—H concentration is smaller than N—H concentration.Type: ApplicationFiled: June 17, 2011Publication date: October 13, 2011Inventors: Mari OTSUKA, Hiroyuki Kamijiyo, Hideaki Harakawa
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Patent number: 7858465Abstract: A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.Type: GrantFiled: February 14, 2008Date of Patent: December 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Toshiaki Komukai, Hideaki Harakawa
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Publication number: 20100140719Abstract: A semiconductor device includes a substrate which includes an element region and an isolation region, a transistor portion which includes a gate insulating film formed on the element region, and a gate electrode having a metal film formed on the gate insulating film and a first semiconductor film formed on the metal film, and a resistance element portion which includes a second semiconductor film formed above the substrate and formed of the same material as that of the first semiconductor film, and a cavity formed between the substrate and the second semiconductor film.Type: ApplicationFiled: September 21, 2009Publication date: June 10, 2010Inventors: Hiroyuki YAMASAKI, Kenji Kojima, Hiroshi Naruse, Hideaki Harakawa
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Publication number: 20100003816Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.Type: ApplicationFiled: September 9, 2009Publication date: January 7, 2010Inventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko
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Patent number: 7605076Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.Type: GrantFiled: February 3, 2006Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko