Patents by Inventor Hideaki Harumoto

Hideaki Harumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020004840
    Abstract: A terminal determines a target value S_target of stream data to be stored in its buffer in relation to its buffer capacity and the transmission capacity of the network. Also, the terminal arbitrarily determines a delay time T_delay from when the terminal writes a head data of the stream data to the buffer to when the terminal reads the data to start playback in a range not exceeding a value obtained by dividing the buffer capacity by the transmission capacity. Those target value and the delay time are then both notified to a server. Based on those notified values, the server controls the transmission speed so that the buffer occupancy Sum of the terminal changes in the vicinity of the target value without exceeding the target value.
    Type: Application
    Filed: July 5, 2001
    Publication date: January 10, 2002
    Inventors: Hideaki Harumoto, Masaki Horiuchi, Takahisa Fujita
  • Patent number: 6009471
    Abstract: A protocol-conforming server system separated into the receive part and the send part and provided with a receive protocol processor for processing the receive and a send protocol processor for processing the send which permits speedy sending out large-sized data which requires to be continuous and consecutive, e.g., moving image data and audio data. Packet header models are provided as template to save processing time, for the data covered by the present invention are sent out in the form of a packet, and almost the same packet header is used each time.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: December 28, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Harumoto, Keiji Okamoto, Yasuhiro Yoshida, Takeshi Omura
  • Patent number: 5978879
    Abstract: A bus bridge apparatus that connects two system buses independent of each other to which a bus arbiter operating independently and located outside of the apparatus, has a function for serving as a master and a slave of the system buses, a base address holding means, and a bus address generating means.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: November 2, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Harumoto, Toshiyuki Ochiai, Taihei Yugawa