Patents by Inventor Hideaki Hayakawa

Hideaki Hayakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9234575
    Abstract: A shift device is provided with a shift lever, a parking switch, and a neutral switch. A transmission is switched to a range, in which the transmission of driving force to driving wheels of a vehicle is started, by the shift lever being operated in two or more directions from a home position and arriving at a specific position. The transmission is switched to a range, in which the transmission of driving force to the driving wheels of the vehicle is interrupted, by the parking switch and the neutral switch being operated in one direction.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: January 12, 2016
    Assignees: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Daisuke Kato, Hideaki Hayakawa, Haruyuki Kodera, Kazumi Endo, Yusuke Nakade, Atsushi Kamada
  • Publication number: 20140144272
    Abstract: A shift device is provided with a shift lever, a parking switch, and a neutral switch. A transmission is switched to a range, in which the transmission of driving force to driving wheels of a vehicle is started, by the shift lever being operated in two or more directions from a home position and arriving at a specific position. The transmission is switched to a range, in which the transmission of driving force to the driving wheels of the vehicle is interrupted, by the parking switch and the neutral switch being operated in one direction.
    Type: Application
    Filed: June 23, 2011
    Publication date: May 29, 2014
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO
    Inventors: Daisuke Kato, Hideaki Hayakawa, Haruyuki Kodera, Kazumi Endo, Yusuke Nakade, Atsushi Kamada
  • Patent number: 7572995
    Abstract: A switch member comprising a convex knob portion on which the finger of an operator catches, wherein the knob portion is retained such that it is pivotable around a pivot shaft, a base surface of the knob portion is configured as a curved convex surface, wherein the curved convex surface is configured as a surface whose radius of curvature gradually becomes larger in a pulling direction of the finger catching on the knob portion, is provided.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: August 11, 2009
    Assignee: Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho
    Inventors: Hideaki Hayakawa, Hidetaka Nomura
  • Publication number: 20070008306
    Abstract: A switch member comprising a convex knob portion on which the finger of an operator catches, wherein the knob portion is retained such that it is pivotable around a pivot shaft, a base surface of the knob portion is configured as a curved convex surface, wherein the curved convex surface is configured as a surface whose radius of curvature gradually becomes larger in a pulling direction of the finger catching on the knob portion, is provided.
    Type: Application
    Filed: July 6, 2006
    Publication date: January 11, 2007
    Applicant: KABUSHIKI KAISHA TOKAI-RIKA-DENKI-SEISAKUSHO
    Inventors: Hideaki Hayakawa, Hidetaka Nomura
  • Publication number: 20030119322
    Abstract: Provided is a method of manufacturing a semiconductor device in which various kinds of processing conditions such as the polishing time in a CMP step can be always provided most appropriate against a wafer of a product lot even if there is an error in the film thickness or the like generated in a CVD step performed prior to the CMP step. The processing conditions in the CMP step are provided based on the film thickness formed in the prior CVD step. Thereby, even if there is an error in the film thickness generated in the CVD step, the processing conditions in the CMP step are provided most appropriate with the consideration of the error. In detail, based on the CVD film thickness and the target value, a processing condition calculator performs calculation of the actual amount of polishing of the present lot. Then, the processing condition calculator performs calculation based on the data, and the searched polishing rate or the searched updated value. Thereby, the polishing time is calculated.
    Type: Application
    Filed: October 3, 2002
    Publication date: June 26, 2003
    Inventors: Toshiya Hirai, Noboru Yokoo, Masahiro Makita, Hideaki Hayakawa, Yasuaki Yamamichi, Akihisa Sakamoto
  • Patent number: 6126511
    Abstract: Disclosed herein is a polishing device including a polishing plate having an upper surface on which a polishing pad is attached, a polishing head having a lower surface opposed to an upper surface of the polishing pad on the polishing plate, for holding a substrate to be polished on the lower surface, and a pressure source for applying a polishing pressure to the polishing head, whereby the substrate held by the polishing head is pressed against the upper surface of the polishing pad under the polishing pressure applied from the pressure source to perform polishing of the substrate. The polishing head is provided with a contact pressure adjusting mechanism capable of adjusting an in-plane contact pressure of the substrate against the upper surface of the polishing pad on the polishing plate at every area of the substrate. Accordingly, the uniformity and the planarity in the plane of the substrate surface to be polished can be improved with a high throughput.
    Type: Grant
    Filed: July 19, 1999
    Date of Patent: October 3, 2000
    Assignee: Sony Corporation
    Inventors: Hideaki Hayakawa, Takatoshi Saito, Yoshiaki Komuro, Shuzo Sato
  • Patent number: 6077155
    Abstract: Disclosed herein is a polishing device including a polishing plate having an upper surface on which a polishing pad is attached, a polishing head having a lower surface opposed to an upper surface of the polishing pad on the polishing plate, for holding a substrate to be polished on the lower surface, and a pressure source for applying a polishing pressure to the polishing head, whereby the substrate held by the polishing head is pressed against the upper surface of the polishing pad under the polishing pressure applied from the pressure source to perform polishing of the substrate. The polishing head is provided with a contact pressure adjusting mechanism capable of adjusting an in-plane contact pressure of the substrate against the upper surface of the polishing pad on the polishing plate at every area of the substrate. Accordingly, the uniformity and the planarity in the plane of the substrate surface to be polished can be improved with a high throughput.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: June 20, 2000
    Assignee: Sony Corporation
    Inventors: Hideaki Hayakawa, Takatoshi Saito, Yoshiaki Komuro, Shuzo Sato
  • Patent number: 5779520
    Abstract: The method and apparatus of polishing and post-processing a substrate by which the particle level after planarization of a semiconductor device by polishing may be reduced. According to the present invention, the substrate of the semiconductor device to be processed is maintained in a wet state since directly after polishing until the end of post-processing.
    Type: Grant
    Filed: July 22, 1997
    Date of Patent: July 14, 1998
    Assignee: Sony Corporation
    Inventor: Hideaki Hayakawa
  • Patent number: 5681212
    Abstract: Disclosed herein is a polishing including a polishing plate having an upper surface on which a polishing pad is attached, a polishing head having a lower surface opposed to an upper surface of the polishing pad on the polishing plate, for holding a substrate to be polished on the lower surface, and a pressure source for applying a polishing pressure to the polishing head, whereby the substrate held by the polishing head is pressed against the upper surface of the polishing pad under the polishing pressure applied from the pressure source to perform polishing of the substrate. The polishing head is provided with a contact pressure adjusting mechanism capable of adjusting an in-plane contact pressure of the substrate against the upper surface of the polishing pad on the polishing plate at every area of the substrate. Accordingly, the uniformity and the planarity in the plane of the substrate surface to be polished can be improved with a high throughput.
    Type: Grant
    Filed: April 5, 1996
    Date of Patent: October 28, 1997
    Assignee: Sony Corporation
    Inventors: Hideaki Hayakawa, Takatoshi Saito, Yoshiaki Komuro, Shuzo Sato
  • Patent number: 5502008
    Abstract: A method of forming a metal plug, including a step of flattening by polishing the surface of a contact plug which is formed by etching back a metal layer, for example, a deposited layer of Blk-W on a substrate. It also makes it possible to print a wiring metal layer by a lithographic process which has thus far been considered difficult to apply to Blk-W. In the method of the invention, a contact hole 3 is opened in an insulation film layer 2 on a substrate 1, and, after coating an adhesion layer 4, a metal layer 5 is deposited on the entire surface. Thereafter, the surface of the metal layer 5 is flattened by a polishing operation, and etched back to form a metal plug 7.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: March 26, 1996
    Assignee: Sony Corporation
    Inventors: Hideaki Hayakawa, Tetsuo Gocho, Junichi Sato
  • Patent number: 5498565
    Abstract: A method of forming trench isolation including a burying step of burying trenches by a deposition means for conducting etching and deposition simultaneously and a polishing step of flattening a burying material by polishing is conducted by disposing an isotropic etching step, a multi-layered etching stopper and a protrusion unifying structure. Polishing can be attained with satisfactory flatness uniformly or with no polishing residue even in a portion to be polished in which the etching stopper layer is distributed unevenly. The method can be applied to manufacture of a semiconductor device or the like.
    Type: Grant
    Filed: November 25, 1992
    Date of Patent: March 12, 1996
    Assignee: Sony Corporation
    Inventors: Tetsuo Gocho, Hideaki Hayakawa
  • Patent number: 5254171
    Abstract: A bias ECR plasma CVD apparatus includes an ECR plasma generating chamber and a plasma CVD chamber for forming a film on a substrate by a plasma CVD reaction. A heating device and a cooling device are provided at least in the vicinity of the substrate for maintaining the substrate and the vicinity thereof at a constant temperature. With this construction, the number of contaminant particles deposited on a surface of the substrate in forming the film on the substrate can be reduced.
    Type: Grant
    Filed: April 13, 1992
    Date of Patent: October 19, 1993
    Assignee: Sony Corporation
    Inventors: Hideaki Hayakawa, Junichi Sato, Tetsuo Gocho
  • Patent number: RE38363
    Abstract: A method of forming trench isolation including a burying step of burying trenches by a deposition means for conducting etching and deposition simultaneously and a polishing step of flattening a burying material by polishing is conducted by disposing an isotropic etching step, a multi-layered etching stopper and a protrusion unifying structure. Polishing can be attained with satisfactory flatness uniformly or with no polishing residue even in a portion to be polished in which the etching stopper layer is distributed unevenly. The method can be applied to manufacture of a semiconductor device or the like.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: December 23, 2003
    Assignee: Sony Corporation
    Inventors: Tetsuo Gocho, Hideaki Hayakawa