Patents by Inventor Hideaki Hirabayashi

Hideaki Hirabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942490
    Abstract: A photon counting radiation detector includes a cell structure including a substrate and an epitaxial layer provided on the substrate, radiation being incident on the epitaxial layer; an inclination ? of the substrate being set in a predetermined range, where tsub is a thickness of the substrate, tepi is a thickness of the epitaxial layer, L is a length of the substrate, and the inclination ? is an inclination of the substrate with respect to an incident direction of the radiation. The epitaxial layer is preferably one type selected from SiC, Ga2O3, GaAs, GaN, diamond, and CdTe. Such a photon counting radiation detector is preferably a direct converting type.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: March 26, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Kuniyuki Kakushima, Akito Sasaki, Atsuya Sasaki, Hideaki Hirabayashi
  • Publication number: 20240079238
    Abstract: A bonded object production method according to an embodiment uses a continuous furnace to process a stacked body including a metal member, a ceramic member, and a brazing material layer located therebetween, while conveying the stacked body; and the method includes a process of heating the stacked body in an inert atmosphere from 200° C. to a bonding temperature at an average temperature raising rate of the stacked body of not less than 15° C./min, a process of bonding the stacked body in an inert atmosphere at the bonding temperature that is within a range of not less than 600° C. and not more than 950° C., and a process of cooling the stacked body from the bonding temperature to 200° C. at an average temperature lowering rate of the stacked body of not less than 15° C./min. A ceramic substrate is favorably a silicon nitride substrate.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 7, 2024
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Hiromasa KATO, Masanori HOSHINO, Hideaki HIRABAYASHI, Seiichi SUENAGA, Kazumitsu MORIMOTO
  • Patent number: 11921428
    Abstract: According to one embodiment, a substrate processing method is disclosed. The method can include treating a substrate with a first liquid. The substrate has a structural body formed on a major surface of the substrate. The method can include forming a support member supporting the structural body by bringing a second liquid into contact with the substrate wetted by the first liquid, and changing at least a portion of the second liquid into a solid by carrying out at least one of causing the second liquid to react, reducing a quantity of a solvent included in the second liquid, and causing at least a portion of a substance dissolved in the second liquid to be separated. The method can include removing the support member by changing at least a part of the support member from a solid phase to a gaseous phase, without passing through a liquid phase.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventors: Yoshihiro Uozumi, Shinsuke Kimura, Yoshihiro Ogawa, Hiroyasu Iimori, Tatsuhiko Koide, Hideaki Hirabayashi, Yuji Nagashima
  • Publication number: 20230390845
    Abstract: According to the embodiment, in a method for manufacturing a ceramic circuit board in which a copper plate is bonded to at least one surface of a ceramic substrate via a brazing material layer, the brazing material layer does not include Ag, but includes Cu, Ti, and one or two of Sn or In, and a ceramic circuit board is prepared in which a portion of the brazing material layer is exposed between the patterned configuration of the copper plate. The method includes a chemical polishing process of chemically polishing the portion of the brazing material layer, and a brazing material etching process of etching the chemically polished portion of the brazing material layer by using an etchant that includes one or two selected from hydrogen peroxide and ammonium peroxodisulfate and has a pH of not more than 6.
    Type: Application
    Filed: August 17, 2023
    Publication date: December 7, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Akito SASAKI, Hiromasa KATO, Hideaki HIRABAYASHI
  • Publication number: 20230345630
    Abstract: According to an embodiment, a ceramic copper circuit board in which the reliability of bonding with a bonding layer is improved is provided, and an insulating circuit board includes an insulating substrate and a conductor part bonded to at least one surface of the insulating substrate. In XPS analysis of a nitrogen amount at the conductor part surface, an average value of the nitrogen amount at any three locations is within a range of not less than 0 at % and not more than 50 at %. In XPS analysis of the oxygen amount at the conductor part surface, the average value of the three locations is favorably within the range of not less than 3 at % and not more than 30 at %. The ratio of the nitrogen amount to the oxygen amount is favorably not less than 0 and not more than 5.
    Type: Application
    Filed: June 22, 2023
    Publication date: October 26, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Kazumitsu MORIMOTO, Hideaki HIRABAYASHI
  • Publication number: 20230335483
    Abstract: According to the embodiment, in an insulating circuit board in which a conductor part is bonded to at least one surface of an insulating substrate, in XPS analysis of the carbon amount at the surface of the conductor part, the average value of the carbon amounts at any three locations is within the range of not less than 0 at % and not more than 70 at %. In XPS analysis of the oxygen amount of the conductor part surface, it is favorable for the average value of any three locations to be within the range of not less than 3 at % and not more than 50 at %.
    Type: Application
    Filed: June 22, 2023
    Publication date: October 19, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Kazumitsu MORIMOTO, Hideaki HIRABAYASHI
  • Patent number: 11600866
    Abstract: A semiconductor solid state battery has an insulating layer provided between an N-type semiconductor and a P-type semiconductor. The first insulating layer preferably has a thickness of 3 nm to 30 ?m and a dielectric constant of 10 or less. The first insulating layer preferably has a density of 60% or more of a bulk body. The semiconductor layer preferably has a capture level introduced. The semiconductor solid state battery can eliminate leakage of an electrolyte solution.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 7, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Materials Co., Ltd.
    Inventors: Atsuya Sasaki, Akito Sasaki, Yoshinori Kataoka, Hideaki Hirabayashi, Shuichi Saito
  • Publication number: 20220181171
    Abstract: According to one embodiment, a substrate processing method is disclosed. The method can include treating a substrate with a first liquid. The substrate has a structural body formed on a major surface of the substrate. The method can include forming a support member supporting the structural body by bringing a second liquid into contact with the substrate wetted by the first liquid, and changing at least a portion of the second liquid into a solid by carrying out at least one of causing the second liquid to react, reducing a quantity of a solvent included in the second liquid, and causing at least a portion of a substance dissolved in the second liquid to be separated. The method can include removing the support member by changing at least a part of the support member from a solid phase to a gaseous phase, without passing through a liquid phase.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Applicant: KIOXIA CORPORATION
    Inventors: Yoshihiro UOZUMI, Shinsuke KIMURA, Yoshihiro OGAWA, Hiroyasu IIMORI, Tatsuhiko KOIDE, Hideaki HIRABAYASHI, Yuji NAGASHIMA
  • Publication number: 20220002166
    Abstract: According to one embodiment, a tungsten oxide powder is provided. The tungsten oxide has an average particle size along a major axis of 10 ?m or less, an average aspect ratio of 10 or less, and 0 to 4 crystal defects per unit area of 9 nm2 on a surface or sectional surface in a direction of a minor axis of a primary particle.
    Type: Application
    Filed: September 21, 2021
    Publication date: January 6, 2022
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Daisuke FUKUSHI, Hideaki HIRABAYASHI, Akito SASAKI, Ryosuke HIRAMATSU, Atsuya SASAKI, Takaki MOROOKA, Yoichiro MORI
  • Patent number: 11211526
    Abstract: A semiconductor light-emitting element having an emission peak wavelength of 395 nm or more and 425 nm or less, comprises: a substrate including a first surface and a second surface, at least one surface selected from the group consisting of the first and second surfaces having an uneven region; a semiconductor layer on the first surface; and a multilayer reflective film on the second surface or the semiconductor layer, wherein the multilayer reflective film includes a structure having a plurality of first dielectric films and a plurality of second dielectric films, the first dielectric films and the second dielectric films being alternately stacked.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: December 28, 2021
    Assignees: TOSHIBA MATERIALS CO., LTD., MEIJO UNIVERSITY
    Inventors: Satoshi Kamiyama, Atsuya Sasaki, Ryosuke Hiramatsu, Hideaki Hirabayashi
  • Patent number: 11211529
    Abstract: A semiconductor light-emitting element according to an embodiment has a light emission peak wavelength not less than 380 nm and not more than 425 nm. The semiconductor light-emitting element includes a stacked structure including a reflective layer, a substrate provided on the reflective layer, and a semiconductor layer provided on the substrate. An uneven structure is provided in a surface of the substrate on the semiconductor layer side. The semiconductor layer includes a buffer layer made of aluminum nitride and having a thickness not less than 10 nm and not more than 100 nm. The buffer layer includes oxygen; and 0.01?O8nm/O3nm?0.5 is satisfied, where O3nm (at %) is the oxygen concentration at a depth of 3 nm of the buffer layer, and O8nm (at %) is the oxygen concentration at a depth of 8 nm of the buffer layer.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: December 28, 2021
    Assignees: TOSHIBA MATERIALS CO., LTD., MEIJO UNIVERSITY
    Inventors: Ryosuke Hiramatsu, Atsuya Sasaki, Hideaki Hirabayashi, Satoshi Kamiyama
  • Patent number: 11129282
    Abstract: According to one embodiment, a method for manufacturing a ceramic circuit board is disclosed. The ceramic circuit board includes a copper plate bonded to at least one surface of a ceramic substrate via a brazing material layer including Ag, Cu, and a reactive metal. The method includes: preparing a ceramic circuit board in which a copper plate is bonded on a ceramic substrate via a brazing material layer, and a portion of the brazing material layer is exposed between a pattern shape of the copper plate; a first chemical polishing process of chemically polishing the portion of the brazing material layer; and a first brazing material etching process of etching the chemically polished portion of the brazing material layer by using an etchant having a pH of 6 or less and including one type or two types selected from hydrogen peroxide and ammonium peroxodisulfate.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: September 21, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Hiromasa Kato, Hideaki Hirabayashi, Fumiyuki Kawashima, Akito Sasaki
  • Publication number: 20210175268
    Abstract: A photon counting radiation detector includes a cell structure including a substrate and an epitaxial layer provided on the substrate, radiation being incident on the epitaxial layer; an inclination ? of the substrate being set in a predetermined range, where tsub is a thickness of the substrate, tepi is a thickness of the epitaxial layer, L is a length of the substrate, and the inclination ? is an inclination of the substrate with respect to an incident direction of the radiation. The epitaxial layer is preferably one type selected from SiC, Ga2O3, GaAs, GaN, diamond, and CdTe. Such a photon counting radiation detector is preferably a direct converting type.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 10, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Kuniyuki KAKUSHIMA, Akito SASAKI, Atsuya SASAKI, Hideaki HIRABAYASHI
  • Patent number: 10964836
    Abstract: According to one embodiment, a photon counting-type radiation detector includes a first cell and a second cell. The first cell transmits radiation. The second cell is stacked with the first cell. The second cell absorbs the radiation passing through the first cell.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: March 30, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD
    Inventors: Kuniyuki Kakushima, Tomoyuki Suzuki, Kazuo Tsutsui, Akito Sasaki, Atsuya Sasaki, Hideaki Hirabayashi, Yoshinori Kataoka
  • Publication number: 20200176633
    Abstract: A semiconductor light-emitting element according to an embodiment has a light emission peak wavelength not less than 380 nm and not more than 425 nm. The semiconductor light-emitting element includes a stacked structure including a reflective layer, a substrate provided on the reflective layer, and a semiconductor layer provided on the substrate. An uneven structure is provided in a surface of the substrate on the semiconductor layer side. The semiconductor layer includes a buffer layer made of aluminum nitride and having a thickness not less than 10 nm and not more than 100 nm. The buffer layer includes oxygen; and 0.01?O8nm/O3nm?0.5 is satisfied, where O3nm (at %) is the oxygen concentration at a depth of 3 nm of the buffer layer, and O8nm (at %) is the oxygen concentration at a depth of 8 nm of the buffer layer.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Applicants: TOSHIBA MATERIALS CO., LTD., Meijo University
    Inventors: Ryosuke HIRAMATSU, Atsuya SASAKI, Hideaki HIRABAYASHI, Satoshi KAMIYAMA
  • Publication number: 20200170118
    Abstract: According to one embodiment, a method for manufacturing a ceramic circuit board is disclosed. The ceramic circuit board includes a copper plate bonded to at least one surface of a ceramic substrate via a brazing material layer including Ag, Cu, and a reactive metal. The method includes: preparing a ceramic circuit board in which a copper plate is bonded on a ceramic substrate via a brazing material layer, and a portion of the brazing material layer is exposed between a pattern shape of the copper plate; a first chemical polishing process of chemically polishing the portion of the brazing material layer; and a first brazing material etching process of etching the chemically polished portion of the brazing material layer by using an etchant having a pH of 6 or less and including one type or two types selected from hydrogen peroxide and ammonium peroxodisulfate.
    Type: Application
    Filed: January 28, 2020
    Publication date: May 28, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Hiromasa KATO, Hideaki HIRABAYASHI, Fumiyuki KAWASHIMA, Akito SASAKI
  • Publication number: 20200048107
    Abstract: According to one embodiment, nano metal compound particles are provided. The nano metal compound particles have an average particle size of 50 nm or less. The nano metal compound particles have a peak ?t of 2.8 eV or less. The peak ?t corresponds to a resonant frequency of an oscillator according to a spectroscopic ellipsometry method fitted to a Lorentz model.
    Type: Application
    Filed: October 22, 2019
    Publication date: February 13, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Yuzo SHIGESATO, Junjun Jia, Daisuke Fukushi, Hideaki Hirabayashi, Yoshinori Kataoka, Akito Sasaki, Atsuya Sasaki
  • Publication number: 20200041663
    Abstract: According to one embodiment, a photon counting-type radiation detector includes a first cell and a second cell. The first cell transmits radiation. The second cell is stacked with the first cell. The second cell absorbs the radiation passing through the first cell.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD
    Inventors: Kuniyuki KAKUSHIMA, Tomoyuki SUZUKI, Kazuo TSUTSUI, Akito SASAKI, Atsuya SASAKI, Hideaki HIRABAYASHI, Yoshinori KATAOKA
  • Publication number: 20200013924
    Abstract: A semiconductor light-emitting element having an emission peak wavelength of 395 nm or more and 425 nm or less, comprises: a substrate including a first surface and a second surface, at least one surface selected from the group consisting of the first and second surfaces having an uneven region; a semiconductor layer on the first surface; and a multilayer reflective film on the second surface or the semiconductor layer, wherein the multilayer reflective film includes a structure having a plurality of first dielectric films and a plurality of second dielectric films, the first dielectric films and the second dielectric films being alternately stacked.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Applicants: TOSHIBA MATERIALS CO., LTD., Meijo University
    Inventors: Satoshi KAMIYAMA, Atsuya SASAKI, Ryosuke HIRAMATSU, Hideaki HIRABAYASHI
  • Publication number: 20190296401
    Abstract: A semiconductor solid state battery has an insulating layer provided between an N-type semiconductor and a P-type semiconductor. The first insulating layer preferably has a thickness of 3 nm to 30 ?m and a dielectric constant of 10 or less. The first insulating layer preferably has a density of 60% or more of a bulk body. The semiconductor layer preferably has a capture level introduced. The semiconductor solid state battery can eliminate leakage of an electrolyte solution.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Atsuya Sasaki, Akito Sasaki, Yoshinori Kataoka, Hideaki Hirabayashi, Shuichi Saito