Patents by Inventor Hideaki Ishino

Hideaki Ishino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240021648
    Abstract: A semiconductor device in which semiconductor layers are stacked is provided. A first structure is arranged between a first semiconductor layer and a second semiconductor layer. A second structure is arranged between the second semiconductor layer and a third semiconductor layer. In an orthographic projection to the third semiconductor layer, a region where elements are arranged in the third semiconductor layer is a first region, and a region between the first region and a peripheral portion of the third semiconductor layer is a second region. In the second region, an opening that extends through the third semiconductor layer, the second structure and the second semiconductor layer and exposes an electrode arranged in the first structure is arranged. Between the first region and the opening, an insulator is arranged at the same height as the second semiconductor layer.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 18, 2024
    Inventors: HIDEAKI ISHINO, JUN YAMAGUCHI, TSUTOMU TANGE, TAKUYA HARA, DAISUKE KOBAYASHI
  • Publication number: 20230387157
    Abstract: A photoelectric conversion device includes a semiconductor substrate, an insulating layer, a light-receiving pixel region, first and second light-shielded regions, and a peripheral region. The insulating layer allows light to pass through the insulating layer. The first light-shielded region includes a light-shielding film formed on the insulating layer. The peripheral region has an opening that penetrates the insulating layer and the semiconductor substrate and exposes a bonding pad of the semiconductor substrate. A first trench is formed in the semiconductor substrate in the second light-shielded region. A second trench is formed in the insulating layer in the second light-shielded region and penetrates the insulating layer. A side face and a bottom face of the second trench are covered with the light-shielding film formed on the insulating layer. In a planar view to the semiconductor substrate, the first trench and the second trench have portions overlapping each other.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 30, 2023
    Inventor: HIDEAKI ISHINO
  • Publication number: 20230317749
    Abstract: A photoelectric conversion device having a first surface and a second surface is provided. A semiconductor layer including a pixel region and a shielded region light-shielded by a shielding layer is arranged between the first surface and the second surface, the shielding layer is arranged between the first surface and the semiconductor layer, and a structure including a pad electrode is arranged between the second surface and the semiconductor layer. The semiconductor layer includes a third surface in contact with the structure and a fourth surface, an opening extending from the first surface to the electrode and a trench extending from the third surface toward the fourth surface are arranged, the trench includes a portion arranged at least between the opening and the pixel region, and the portion is arranged so as to overlap the light shielding layer.
    Type: Application
    Filed: March 22, 2023
    Publication date: October 5, 2023
    Inventor: HIDEAKI ISHINO
  • Patent number: 11742373
    Abstract: A semiconductor device in which a first chip and a second chip are stacked including a first wiring line and a second wiring line by which the first chip and the second chip are electrically connected. The first wiring line and the second wiring line each include a bonding portion for bonding one of a plurality of conductive patterns placed in the first chip and one of a plurality of conductive patterns placed in the second chip. The number of bonding portions included in the first wiring line is larger than the number of bonding portions included in the second wiring line.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: August 29, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Ryoki, Hirofumi Totsuka, Masahiro Kobayashi, Hideaki Ishino, Hiroaki Kobayashi
  • Publication number: 20230074553
    Abstract: An apparatus comprising a semiconductor arranged with a pixel region and a shielding region is provided. The shielding region includes a first region having first and second trenches and a second region arranged between the first region and the pixel region. The first trench extends from a first surface of the semiconductor toward a second surface of the semiconductor and the second trench extends from the second surface toward the first surface. (D/2)?(T1, T2)<D is satisfied, where T1 and T2 are depth of the first and second trenches and D is a thickness of the semiconductor. The first and second trenches are arranged apart from each other, and the first and second trenches overlap at least partly in an orthogonal projection with respect to a boundary surface between the first and second regions.
    Type: Application
    Filed: August 25, 2022
    Publication date: March 9, 2023
    Inventor: Hideaki Ishino
  • Patent number: 11355658
    Abstract: A method of manufacturing an imaging apparatus includes: preparing a substrate comprising a wafer and a silicon layer arranged on the wafer, the wafer including a first semiconductor region made of single crystal silicon with an oxygen concentration not less than 2×1016 atoms/cm3 and not greater than 4×1017 atoms/cm3, the silicon layer including a second semiconductor region made of single crystal silicon with an oxygen concentration lower than the oxygen concentration in the first semiconductor region; annealing the substrate in an atmosphere containing oxygen and setting the oxygen concentration in the second semiconductor region within the range not less than 2×1016 atoms/cm3 and not greater than 4×1017 atoms/cm3; and forming a photoelectric conversion element in the second semiconductor region after the annealing.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: June 7, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Toshihiro Shoyama, Hiroshi Takakusagi, Yasuo Yamazaki, Hideaki Ishino, Toshiyuki Ogawa
  • Patent number: 11329088
    Abstract: A semiconductor apparatus includes a semiconductor layer having first and second faces, a semiconductor element portion in which semiconductor elements are provided, and openings each penetrating the semiconductor layer from the second face side, an interconnection structure provided on the first face side, and an insulator portion provided to surround at least one of the openings within a virtual plane along the second face and extend to a depth between T/2 and T from the first face, where T is the thickness of the semiconductor layer. The semiconductor layer includes a semiconductor region of one conductivity type provided on the opposite side to the one opening to the insulator portion within the virtual plane, and a semiconductor region of another conductivity type provided in the semiconductor layer from the insulator portion face on the second face side to the second face in a direction perpendicular to the second face.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: May 10, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideaki Ishino
  • Patent number: 11276723
    Abstract: A semiconductor device comprising: a substrate; a semiconductor layer; and a wiring structure section between the substrate and the semiconductor layer, the wiring structure section including a plurality of stacked wiring layers and a plurality of stacked insulating films, the wiring structure section including an electrode, wherein an opening for connecting a member to the electrode is formed in the semiconductor layer and the wiring structure section; the semiconductor layer has an isolation region in which an insulating film is embedded and which surrounds the opening; the wiring structure section has a ring which is formed of the plurality of wiring layers and surround the opening; and a distance between the opening and the ring closest to the opening is larger than a distance between the opening and the isolation region closest to the opening.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: March 15, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takumi Ogino, Hideaki Ishino, Akihiro Shimizu, Katsunori Hirota, Tsutomu Tange
  • Publication number: 20210327939
    Abstract: The distance between an upper end of a light-shielding portion and a photoelectric conversion layer is longer than the distance between the lower surface of a light-shielding film and the photoelectric conversion layer. The distance between a lower end of the light-shielding portion and the photoelectric conversion layer is shorter than the distance between the lower surface of the light-shielding film and the photoelectric conversion layer. In a plane including the light-shielding film and the light-shielding portion, an opening defined by the light-shielding portion and a gap between the light-shielding portion and the light-shielding film are provided, and the width of the gap is smaller than the width of the opening.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 21, 2021
    Inventors: Kenji Togo, Hideaki Ishino, Yoshiyuki Hayashi
  • Publication number: 20210313369
    Abstract: A technique advantageous for improving an optical property of a photoelectric conversion apparatus is provided. The photoelectric conversion apparatus includes a photoelectric conversion layer and a light-shielding film that covers the photoelectric conversion layer, wherein the light-shielding film includes one metallic layer and another metallic layer located between the one metallic layer and the photoelectric conversion layer.
    Type: Application
    Filed: April 5, 2021
    Publication date: October 7, 2021
    Inventors: Tsutomu Tange, Toshiyuki Ogawa, Hideaki Ishino, Yusuke Onuki
  • Patent number: 11114484
    Abstract: A photoelectric conversion apparatus includes, a semiconductor substrate having a photoelectric conversion unit performing photoelectric conversion on entering light and accumulating first electric charges, a first transistor electrically connected to the photoelectric conversion unit and having a first gate on a second surface, and a second transistor having a second gate shorter than the first gate on the second surface, a first fixed charge film continuously provided directly or with an insulating film in between in an area overlapping the photoelectric conversion unit on a first surface and the second transistor, the first fixed charge film having fixed charges of the first polarity, and a second fixed charge film provided directly or with an insulating film in between in an area overlapping the second transistor and the first fixed charge film, the second fixed charge film having fixed charges of a second polarity.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 7, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takumi Ogino, Hideaki Ishino
  • Publication number: 20210167109
    Abstract: A photoelectric conversion device having a light-receiving pixel region and a light-shielded pixel region, the photoelectric conversion device comprising: a semiconductor layer; a first layered structure which is arranged on a first surface of the semiconductor layer in the light-receiving pixel region and in which at least an insulating layer and a metal oxide layer arranged between the semiconductor layer and the insulating layer are stacked; and a second layered structure which is arranged on the first surface of the semiconductor layer in the light-shielded pixel region and in which at least a light-shielding layer, a metal oxide layer arranged between the semiconductor layer and the light-shielding layer, a first insulating layer arranged between the metal oxide layer and the light-shielding layer, and a second insulating layer arranged between the first insulating layer and the light-shielding layer and including hydrogen are stacked.
    Type: Application
    Filed: November 12, 2020
    Publication date: June 3, 2021
    Inventor: Hideaki Ishino
  • Publication number: 20210167113
    Abstract: A semiconductor device in which a first chip and a second chip are stacked including a first wiring line and a second wiring line by which the first chip and the second chip are electrically connected. The first wiring line and the second wiring line each include a bonding portion for bonding one of a plurality of conductive patterns placed in the first chip and one of a plurality of conductive patterns placed in the second chip. The number of bonding portions included in the first wiring line is larger than the number of bonding portions included in the second wiring line.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Inventors: Tatsuya Ryoki, Hirofumi Totsuka, Masahiro Kobayashi, Hideaki Ishino, Hiroaki Kobayashi
  • Patent number: 10957732
    Abstract: A semiconductor device in which a first chip and a second chip are stacked including a first wiring line and a second wiring line by which the first chip and the second chip are electrically connected. The first wiring line and the second wiring line each include a bonding portion for bonding one of a plurality of conductive patterns placed in the first chip and one of a plurality of conductive patterns placed in the second chip. The number of bonding portions included in the first wiring line is larger than the number of bonding portions included in the second wiring line.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: March 23, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Ryoki, Hirofumi Totsuka, Masahiro Kobayashi, Hideaki Ishino, Hiroaki Kobayashi
  • Publication number: 20200343280
    Abstract: A semiconductor apparatus includes a semiconductor layer having first and second faces, a semiconductor element portion in which semiconductor elements are provided, and openings each penetrating the semiconductor layer from the second face side, an interconnection structure provided on the first face side, and an insulator portion provided to surround at least one of the openings within a virtual plane along the second face and extend to a depth between T/2 and T from the first face, where T is the thickness of the semiconductor layer. The semiconductor layer includes a semiconductor region of one conductivity type provided on the opposite side to the one opening to the insulator portion within the virtual plane, and a semiconductor region of another conductivity type provided in the semiconductor layer from the insulator portion face on the second face side to the second face in a direction perpendicular to the second face.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 29, 2020
    Inventor: Hideaki Ishino
  • Publication number: 20200274006
    Abstract: A method of manufacturing an imaging apparatus includes: preparing a substrate comprising a wafer and a silicon layer arranged on the wafer, the wafer including a first semiconductor region made of single crystal silicon with an oxygen concentration not less than 2×1016 atoms/cm3 and not greater than 4×1017 atoms/cm3, the silicon layer including a second semiconductor region made of single crystal silicon with an oxygen concentration lower than the oxygen concentration in the first semiconductor region; annealing the substrate in an atmosphere containing oxygen and setting the oxygen concentration in the second semiconductor region within the range not less than 2×1016 atoms/cm3 and not greater than 4×1017 atoms/cm3; and forming a photoelectric conversion element in the second semiconductor region after the annealing.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Toshihiro Shoyama, Hiroshi Takakusagi, Yasuo Yamazaki, Hideaki Ishino, Toshiyuki Ogawa
  • Patent number: 10693023
    Abstract: A method of manufacturing an imaging apparatus includes: preparing a substrate comprising a wafer and a silicon layer arranged on the wafer, the wafer including a first semiconductor region made of single crystal silicon with an oxygen concentration not less than 2×1016 atoms/cm3 and not greater than 4×1017 atoms/cm3, the silicon layer including a second semiconductor region made of single crystal silicon with an oxygen concentration lower than the oxygen concentration in the first semiconductor region; annealing the substrate in an atmosphere containing oxygen and setting the oxygen concentration in the second semiconductor region within the range not less than 2×1016 atoms/cm3 and not greater than 4×1017 atoms/cm3; and forming a photoelectric conversion element in the second semiconductor region after the annealing.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 23, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Toshihiro Shoyama, Hiroshi Takakusagi, Yasuo Yamazaki, Hideaki Ishino, Toshiyuki Ogawa
  • Publication number: 20200127032
    Abstract: A semiconductor device comprising: a substrate; a semiconductor layer; and a wiring structure section between the substrate and the semiconductor layer, the wiring structure section including a plurality of stacked wiring layers and a plurality of stacked insulating films, the wiring structure section including an electrode, wherein an opening for connecting a member to the electrode is formed in the semiconductor layer and the wiring structure section; the semiconductor layer has an isolation region in which an insulating film is embedded and which surrounds the opening; the wiring structure section has a ring which is formed of the plurality of wiring layers and surround the opening; and a distance between the opening and the ring closest to the opening is larger than a distance between the opening and the isolation region closest to the opening.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 23, 2020
    Inventors: Takumi Ogino, Hideaki Ishino, Akihiro Shimizu, Katsunori Hirota, Tsutomu Tange
  • Patent number: 10622397
    Abstract: A semiconductor layer includes an opening, and in a joint surface between structures, a portion between a semiconductor layer and an opening in a direction in which the semiconductor layers are stacked together includes a plurality of conductor portions and an insulator portion located between the plurality of conductor portions in a direction orthogonal to the direction.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: April 14, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hideaki Ishino, Takumi Ogino
  • Publication number: 20190371836
    Abstract: A photoelectric conversion apparatus includes, a semiconductor substrate having a photoelectric conversion unit performing photoelectric conversion on entering light and accumulating first electric charges, a first transistor electrically connected to the photoelectric conversion unit and having a first gate on a second surface, and a second transistor having a second gate shorter than the first gate on the second surface, a first fixed charge film continuously provided directly or with an insulating film in between in an area overlapping the photoelectric conversion unit on a first surface and the second transistor, the first fixed charge film having fixed charges of the first polarity, and a second fixed charge film provided directly or with an insulating film in between in an area overlapping the second transistor and the first fixed charge film, the second fixed charge film having fixed charges of a second polarity.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 5, 2019
    Inventors: Takumi Ogino, Hideaki Ishino