Abstract: A processing unit reads out design information about a highest hierarchical layer from a storage unit, divides the highest hierarchical layer into a plurality of segments (segments, etc.) based on the design information about the highest hierarchical layer, detects overlapping areas (optimum placement areas) in which segments at a corresponding location among a plurality of instances in a lowest hierarchical layer included in the highest hierarchical layer overlap with each other at least partly when the plurality of instances are overlapped with each other, sets, in each of the overlapping areas in the plurality of instances, a temporary placement location in which a test cell used for testing of manufacturing variation in critical dimension is temporarily placed, and outputs information indicating the overlapping areas and the temporary placement locations.

Abstract: There is provided a design support apparatus including a memory, and a processor coupled to the memory and the processor configured to obtain an arrangement target cell, and arrange the arrangement target cell at a position satisfying a condition of an arrangement position recommended for each cell when the arrangement target cell is arranged, based on definition information for defining the condition.

Abstract: There is provided a design support apparatus including a memory, and a processor coupled to the memory and the processor configured to obtain an arrangement target cell, and arrange the arrangement target cell at a position satisfying a condition of an arrangement position recommended for each cell when the arrangement target cell is arranged, based on definition information for defining the condition.

Abstract: A present design support method includes: arranging capacitance cells in an entire area of a cell arrangement area of a semiconductor integrated circuit , before arranging logic cells; upon detecting that a position at which a certain logic cell will be arranged is designated, calculating a total sum of capacitance for a first capacitance check area that includes the position among plural capacitance check areas that are included in the cell arrangement area, while assuming that a capacitance cell at the position is removed; calculating a total sum of necessary capacitance for the first capacitance check area, while assuming that the certain logic cell is arranged at the position and outputting information that represents a relationship between the total sum of capacitance and the total sum of necessary capacitance for the first capacitance check area.

Abstract: An automatic wiring method includes calculating a metal area within an integrated circuit, and determining whether the metal area calculated at the calculating is smaller than a minimum metal area as a predetermined threshold value.

Abstract: A design support apparatus that supports designing of a circuit and is connected to a display unit, the design support apparatus includes a storage unit that stores logical connection information of the circuit and cell information of a plurality of cells included in the circuit, a selection unit that selects target cell information of a cell to be placed out of the cell information stored in the storage unit, a placement unit that provisionally places the cell corresponding to the selected target cell information based on inputted positional information, a determination unit that determines whether a wiring mode is set, a wiring unit that provisionally arranges wiring connected to the provisionally placed cell when the determination unit determines that the wiring mode is set, and a finalization unit that finalizes a position of the wiring provisionally arranged based on finalization of a position of the cell provisionally placed.

Abstract: A circuit design assisting apparatus for assisting designing of a circuit is provided. The apparatus includes a storage unit that stores information regarding a configuration of components used in a design-target circuit and wirings between the components, an acquiring unit that acquires label setting information that associates a label with the configuration information indicating the components of the design-target circuit and the wirings between the components, a selecting unit that selects, from the storage unit, information having a configuration that matches the configuration information included in the acquired label setting information. and a setting unit that sets a label that is associated with the configuration information by the acquired label setting information to the information selected by the selecting unit and registering the set label in the storage unit.

Abstract: A design support apparatus includes a database storage storing a first database including respective logical connection information for a first-layer circuit and a second-layer circuit laid lower than the first-layer circuit, both provided in a circuit under design, a file generator that traces logical connection type identification information identifying types of logical connections from the first-layer circuit to the second-layer circuit based on the logical connection information included in the first database, and generates a layer terminal information file including layer terminal code information associating layer terminals in the second-layer circuit with layer terminal codes having trace information regarding the logical connection type identification information, and a database generator that generates a second database based on the generated layer terminal information file for the second-layer circuit including placement information for a plurality of cells included in the circuit and wiring inform

Abstract: A design support apparatus includes a database storage storing a first database including respective logical connection information for a first-layer circuit and a second-layer circuit laid lower than the first-layer circuit, both provided in a circuit under design, a file generator that traces logical connection type identification information identifying types of logical connections from the first-layer circuit to the second-layer circuit based on the logical connection information included in the first database, and generates a layer terminal information file including layer terminal code information associating layer terminals in the second-layer circuit with layer terminal codes having trace information regarding the logical connection type identification information, and a database generator that generates a second database based on the generated layer terminal information file for the second-layer circuit including placement information for a plurality of cells included in the circuit and wiring inform

Abstract: A design support apparatus that supports designing of a circuit and is connected to a display unit, the design support apparatus includes a storage unit that stores logical connection information of the circuit and cell information of a plurality of cells included in the circuit, a selection unit that selects target cell information of a cell to be placed out of the cell information stored in the storage unit, a placement unit that provisionally places the cell corresponding to the selected target cell information based on inputted positional information, a determination unit that determines whether a wiring mode is set, a wiring unit that provisionally arranges wiring connected to the provisionally placed cell when the determination unit determines that the wiring mode is set, and a finalization unit that finalizes a position of the wiring provisionally arranged based on finalization of a position of the cell provisionally placed.

Abstract: An automatic wiring method includes calculating a metal area within an integrated circuit, and determining whether the metal area calculated at the calculating is smaller than a minimum metal area as a predetermined threshold value.

Abstract: A circuit design assisting apparatus for assisting designing of a circuit is provided. The apparatus includes a storage unit that stores information regarding a configuration of components used in a design-target circuit and wirings between the components, an acquiring unit that acquires label setting information that associates a label with the configuration information indicating the components of the design-target circuit and the wirings between the components, a selecting unit that selects, from the storage unit, information having a configuration that matches the configuration information included in the acquired label setting information. and a setting unit that sets a label that is associated with the configuration information by the acquired label setting information to the information selected by the selecting unit and registering the set label in the storage unit.

Abstract: A problem is efficiently solved by giving a proper adjacent spacing condition only to nets having such a problem that a wiring delay and crosstalks are caused. A wiring processing unit executes a wiring process by giving a first adjacent spacing condition that does not become a wiring violation on the basis of a net list of a semiconductor circuit. A noise analyzing unit extracts error nets in which noise errors have occurred by a noise analysis of a wiring formed by the wiring processing unit. A wiring condition changing unit gives a second adjacent spacing condition for eliminating the noise errors to the error nets extracted by the noise analyzing unit, gives the first adjacent spacing condition to the nets other than the error nets, and allows the wiring process to be executed again on the basis of the net list.

Abstract: In addition to a rectangular shape, a non-rectangular shape is enabled to be handled as a physical design unit, thereby miniaturizing a chip and reducing the costs. A floor plan processing unit forms a floor plan for arranging a plurality of circuit blocks including a non-rectangular area into the chip. A layout processing unit divides each of a plurality of non-rectangular circuit blocks having non-rectangular areas into a plurality of rectangular areas and arranges them into the chip so as to be adapted to the floor plan. A wiring processing unit mutually wires the plurality of circuit blocks. The non-rectangular area is constructed by a set of a plurality of division rectangular areas and has a data structure showing a set of two-dimensional coordinate values indicating diagonal vertices of the plurality of division rectangular areas. The non-rectangular areas are also introduced with respect to the cells which are arranged in the circuit block.

Abstract: When one net is wired, by restricting a wiring area, the net is efficiently wired in a short time. A wiring area setting unit sets a maximum rectangle including a set of terminals constructing the net into a wiring area. A wiring deciding unit decides the wiring between the nets so as to realize the shortest distance for the wiring area as a target. If a wiring violation or a non-connected terminal exists, a wiring area enlarging unit enlarges the present wiring area in accordance with a preset parameter and, thereafter, allows the wiring deciding unit to decide the wiring. With respect to a clip net in which in the case where one of a plurality of input terminals having the same function of cells is used, the non-used input terminals are wired as clip terminals to power terminals as well, a cell area is set into a wiring area and wired and if the wiring violation or non-connected clip terminal exists, the present wiring area is enlarged and the wiring is repeated.

Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.

Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.

Abstract: When one net is wired, by restricting a wiring area, the net is efficiently wired in a short time. A wiring area setting unit sets a maximum rectangle including a set of terminals constructing the net into a wiring area. A wiring deciding unit decides the wiring between the nets so as to realize the shortest distance for the wiring area as a target. If a wiring violation or a non-connected terminal exists, a wiring area enlarging unit enlarges the present wiring area in accordance with a preset parameter and, thereafter, allows the wiring deciding unit to decide the wiring. With respect to a clip net in which in the case where one of a plurality of input terminals having the same function of cells is used, the non-used input terminals are wired as clip terminals to power terminals as well, a cell area is set into a wiring area and wired and if the wiring violation or non-connected clip terminal exists, the present wiring area is enlarged and the wiring is repeated.

Abstract: In addition to a rectangular shape, a non-rectangular shape is enabled to be handled as a physical design unit, thereby miniaturizing a chip and reducing the costs. A floor plan processing unit forms a floor plan for arranging a plurality of circuit blocks including a non-rectangular area into the chip. A layout processing unit divides each of a plurality of non-rectangular circuit blocks having non-rectangular areas into a plurality of rectangular areas and arranges them into the chip so as to be adapted to the floor plan. A wiring processing unit mutually wires the plurality of circuit blocks. The non-rectangular area is constructed by a set of a plurality of division rectangular areas and has a data structure showing a set of two-dimensional coordinate values indicating diagonal vertices of the plurality of division rectangular areas. The non-rectangular areas are also introduced with respect to the cells which are arranged in the circuit block.

Abstract: A problem is efficiently solved by giving a proper adjacent spacing condition only to nets having such a problem that a wiring delay and crosstalks are caused. A wiring processing unit executes a wiring process by giving a first adjacent spacing condition that does not become a wiring violation on the basis of a net list of a semiconductor circuit. A noise analyzing unit extracts error nets in which noise errors have occurred by a noise analysis of a wiring formed by the wiring processing unit. A wiring condition changing unit gives a second adjacent spacing condition for eliminating the noise errors to the error nets extracted by the noise analyzing unit, gives the first adjacent spacing condition to the nets other than the error nets, and allows the wiring process to be executed again on the basis of the net list.