Abstract: A trimming method for adjusting electrical characteristics of an adjustment circuit, which is provided in a semiconductor substrate, by cutting a fuse resistor provided in the semiconductor substrate. In a case where a cutting current flows to the fuse resistor to cut the fuse resistor, at least one of switching devices provided in the semiconductor substrate is set to a conductible state to make the cutting current flow to the switching device.

Abstract: A semiconductor device includes: a semiconductor base body of a first conductivity type; a high-potential-side terminal connected to the semiconductor base body; a horizontal control circuit element deposited at an upper part of the semiconductor base body; a signal input terminal connected to a control electrode of the control circuit element; a low-potential-side terminal connected to a main electrode region of the control circuit element; an input-side diode connected in a forward direction between the signal input terminal and the semiconductor base body; and a vertical protective element connected between the semiconductor base body and the low-potential-side terminal.

Abstract: A trimming method for adjusting electrical characteristics of an adjustment circuit, which is provided in a semiconductor substrate, by cutting a fuse resistor provided in the semiconductor substrate. In a case where a cutting current flows to the fuse resistor to cut the fuse resistor, at least one of switching devices provided in the semiconductor substrate is set to a conductible state to make the cutting current flow to the switching device.

Abstract: A semiconductor integrated circuit includes: a semiconductor monocrystalline region; an insulating film provided on a main surface of the semiconductor monocrystalline region; a conductive layer having a rectangular shape provided on the insulating film and including at least a polycrystalline layer of p-type; electric-field relaxing layers having a lower specific resistivity than the conductive layer and each including a polycrystalline layer of n-type so as to be arranged on both sides of the conductive layer in a direction perpendicular to a current-flowing direction; a high-potential-side electrode in ohmic contact with the conductive layer at one end of the conductive layer in the current-flowing direction; and a low-potential-side electrode in ohmic contact with the conductive layer and the respective electric-field relaxing layers at another end of the conductive layer opposed to the one end in the current-flowing direction, and having a lower potential than the high-potential-side electrode.

Abstract: In a method of manufacturing a semiconductor device, selectively forming a first semiconductor region and a fourth semiconductor region to be away from each other in a surface layer of a first principal surface of a semiconductor substrate at a same impurity implantation and impurity diffusion process, selectively forming a second semiconductor region in the first semiconductor region and selectively forming a fifth semiconductor region in the fourth semiconductor region at a same impurity implantation and impurity diffusion process, and selectively forming a third semiconductor region that penetrates the first semiconductor region in a depth direction and selectively forming a sixth semiconductor region that penetrates the fourth semiconductor region in the depth direction at a same impurity implantation and impurity diffusion process.

Abstract: In a method of manufacturing a semiconductor device, selectively forming a first semiconductor region and a fourth semiconductor region to be away from each other in a surface layer of a first principal surface of a semiconductor substrate at a same impurity implantation and impurity diffusion process, selectively forming a second semiconductor region in the first semiconductor region and selectively forming a fifth semiconductor region in the fourth semiconductor region at a same impurity implantation and impurity diffusion process, and selectively forming a third semiconductor region that penetrates the first semiconductor region in a depth direction and selectively forming a sixth semiconductor region that penetrates the fourth semiconductor region in the depth direction at a same impurity implantation and impurity diffusion process.

Abstract: A semiconductor integrated circuit includes: a semiconductor monocrystalline region; an insulating film provided on a main surface of the semiconductor monocrystalline region; a conductive layer having a rectangular shape provided on the insulating film and including at least a polycrystalline layer of p-type; electric-field relaxing layers having a lower specific resistivity than the conductive layer and each including a polycrystalline layer of n-type so as to be arranged on both sides of the conductive layer in a direction perpendicular to a current-flowing direction; a high-potential-side electrode in ohmic contact with the conductive layer at one end of the conductive layer in the current-flowing direction; and a low-potential-side electrode in ohmic contact with the conductive layer and the respective electric-field relaxing layers at another end of the conductive layer opposed to the one end in the current-flowing direction, and having a lower potential than the high-potential-side electrode.

Abstract: In a circuit portion, a p+-type diffusion region penetrates, in the depth direction, an n?-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p++-type contact region, an n+-type diffusion region, and a p+-type diffusion region are selectively provided in a p+-type diffusion region on the front side of the base substrate. The p+-type diffusion region penetrates the p?-type diffusion region in the depth direction, on the outer periphery of the p?-type diffusion region. An n+-type source region, the p+-type diffusion region, the p++-type contact region, and the n+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.

Abstract: A p+-type anode region that forms a contact of an anode electrode on a front surface of a semiconductor substrate and a p+-type starting substrate of a rear surface of the semiconductor substrate is formed on the front surface of the semiconductor substrate, whereby an up-anode type vertical diode is configured. The semiconductor substrate has a p?-type epitaxial layer stacked on the p+-type starting substrate, and a p-type transition layer in a surface layer of the p?-type epitaxial layer, facing the p+-type starting substrate. A p-type anode diffusion region is provided between a p+-type surface anode region and the p-type transition layer, and contacts the p+-type surface anode region and the p-type transition layer. A p-type impurity concentration of the p-type anode diffusion region decreases from an interface with the p+-type surface anode region toward an interface with the p-type transition layer.

Abstract: A semiconductor device includes: a channel-forming region of a first conductivity type; a first main electrode region of a second conductivity type disposed in a portion of an upper part of the channel-forming region; a drift region of the second conductivity type that is disposed in an upper part of the channel-forming region apart from the first main electrode region; a second main electrode region of the second conductivity type that is disposed in a part of an upper part of the drift region; and a stopper region of the second conductivity type that is disposed at an end region of the drift region apart from the first main electrode region and has a higher concentration than the drift region. The stopper region restricts extension of a depletion layer developing at the boundary of the pn junction between the channel-forming region and the drift region.

Abstract: In a circuit portion, a p+-type diffusion region penetrates, in the depth direction, an n?-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p++-type contact region, an n+-type diffusion region, and a p+-type diffusion region are selectively provided in a p+-type diffusion region on the front side of the base substrate. The p+-type diffusion region penetrates the p?-type diffusion region in the depth direction, on the outer periphery of the p?-type diffusion region. An n+-type source region, the p+-type diffusion region, the p++-type contact region, and the n+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.

Abstract: A semiconductor device includes a first insulating film on a semiconductor substrate; a fuse on the first insulating film, including first second terminal pads, a blowing strip having a width smaller than the first and second terminal pads, extending from the first terminal pad to the second terminal pad, a first connecting portion connecting the first terminal pad and the blowing strip, and a second connecting portion connecting the second terminal pad and the blowing strip, and a second insulating film covering the first insulating film and the fuse. The first and second connecting portions are asymmetric with respect to a reference plane passing through the middle point of the blowing strip, orthogonal to the extending direction of the blowing strip and normal to the principal surface of the semiconductor substrate.

Abstract: A p+-type anode region that forms a contact of an anode electrode on a front surface of a semiconductor substrate and a p+-type starting substrate of a rear surface of the semiconductor substrate is formed on the front surface of the semiconductor substrate, whereby an up-anode type vertical diode is configured. The semiconductor substrate has a p?-type epitaxial layer stacked on the p+-type starting substrate, and a p-type transition layer in a surface layer of the p?-type epitaxial layer, facing the p+-type starting substrate. A p-type anode diffusion region is provided between a p+-type surface anode region and the p-type transition layer, and contacts the p+-type surface anode region and the p-type transition layer. A p-type impurity concentration of the p-type anode diffusion region decreases from an interface with the p+-type surface anode region toward an interface with the p-type transition layer.

Abstract: In a circuit portion, a p+-type diffusion region penetrates, in the depth direction, an n?-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p++-type contact region, an n+-type diffusion region, and a p+-type diffusion region are selectively provided in a p+-type diffusion region on the front side of the base substrate. The p+-type diffusion region penetrates the p?-type diffusion region in the depth direction, on the outer periphery of the p?-type diffusion region. An n+-type source region, the p+-type diffusion region, the p++-type contact region, and the n+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.

Abstract: A semiconductor device includes a lateral MOSFET and a vertical semiconductor device that are formed on the same semiconductor substrate. In the lateral MOSFET, the voltage of a back-gate electrode is set to be higher than the voltage of a source electrode and a gate electrode by greater than or equal to a prescribed value (greater than or equal to 40V). A drain-side diffusion region, a drain diffusion region, a drain electrode, a gate insulating film, a gate electrode, and a LOCOS film are formed in annular shapes centered on a source diffusion region. As a result, an active channel region between the drain diffusion region and the source diffusion region as well as peripheral portions of the LOCOS film are also annular-shaped.

Abstract: Current detection circuit of a semiconductor device provided with a shunt resistor, a voltage division ratio adjustment resistor and a selection circuit which selects a voltage division ratio of the latter and has enhancement type MOSFETs and Zener Zaps as trimming elements. One of the Zener Zaps is trimmed and a divided voltage of the voltage division ratio adjustment resistor connected in parallel with the shunt resistor is outputted. The detected voltage in which variation of the resistance of the shunt resistor has been cancelled is therefore outputted. As the shunt resistor and the voltage division ratio adjustment resistor are laminated together, it is possible to obtain a current detection circuit with a small area, which can detect a current flowing into a shunt resistor with high accuracy.

Abstract: A semiconductor device and a method for testing the semiconductor device are provided. The semiconductor device includes a diode (protection element) and a semiconductor element having a withstand voltage that is higher than that of the diode provided on one and the same first-conductive-type semiconductor substrate, the diode having a second-conductive-type first semiconductor region selectively provided in a front surface layer of the semiconductor substrate. A high concentration region is open in a normal time, but is short-circuited to a potential higher than that of a GND pad through a second wiring layer in a screening test time. Thus, a semiconductor device and a method for testing the semiconductor device are provided, in which a protection element can be prevented from breaking down and initial failure of a device which is formed on one and the same semiconductor substrate as the protection element can be detected accurately.

Abstract: In a circuit portion, a p+-type diffusion region penetrates, in the depth direction, an n?-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p++-type contact region, an n+-type diffusion region, and a p+-type diffusion region are selectively provided in a p+-type diffusion region on the front side of the base substrate. The p+-type diffusion region penetrates the p?-type diffusion region in the depth direction, on the outer periphery of the p?-type diffusion region. An n+-type source region, the p+-type diffusion region, the p++-type contact region, and the n+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.

Abstract: One embodiment includes a vertical n-channel power MOSFET for an output stage and a horizontal p-channel MOSFET for controlling the vertical n-channel power MOSFET are disposed on a single semiconductor substrate. The horizontal p-channel MOSFET has Psd (a p+-type source region and a p+-type drain region) formed in a self-aligning manner at a gate electrode. The Psd has p+-type diffusion regions disposed therein causing the Psd to partially have a high impurity concentration. The p+-type diffusion regions are connected to respective metal wiring layers through contact holes that are formed by ion implantation concurrently with a p+-type diffusion region of the vertical n-channel power MOSFET and that have a width narrower than conventional contact holes. In this way, contact properties can be improved between the metal wiring layer and a semiconductor portion and size reductions can be achieved.

Abstract: In a semiconductor device such as a three-phase one-chip gate driver IC, HVNMOSs configuring two set and reset level shift circuits are disposed on non-opposed surfaces, and it is thereby possible to reduce the amount of electrons flowing into drains of HVNMOSs of another phase due to a negative voltage surge. Also, distances from an opposed surface on the opposite side to the respective drains of the HVNMOSs configuring the two set and reset level shift circuits are made equal to or more than 150 ?m, and it is thereby possible to prevent a malfunction of a high side driver circuit of another phase to which no negative surge is applied.