Patents by Inventor Hideaki Kurita
Hideaki Kurita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967944Abstract: The vibrator element includes a vibrating arm provided with an arm part, and a weight part which has a weight, the weight is provided with at least one processing scar, when an axis which overlaps a center in a width direction of the vibrating arm, and which extends along an extending direction of the vibrating arm is a central axis, and an axis which overlaps a centroid of the vibrating arm, and which extends along the extending direction of the vibrating arm is a centroid axis, the processing scar is formed in at least an area at an opposite side to the centroid axis, and S1<S2 an area of the processing scar located at the centroid axis side with respect to the central axis is S1, and an area of the processing scar located at an opposite side to the centroid axis with respect to the central axis is S2.Type: GrantFiled: February 18, 2021Date of Patent: April 23, 2024Assignee: SEIKO EPSON CORPORATIONInventor: Hideaki Kurita
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Publication number: 20220040684Abstract: A cation-exchange membrane including: layer (I) containing repeating units (A) each represented by formula (1) and repeating units (S) each containing a sulfonic acid-type ion-exchange group, wherein the mass proportion of repeating units (A) based on the total mass proportion of repeating units (A) and repeating units (S) being 100% by mass is 53% by mass or more and 70% by mass or less; and layer (II) containing a fluorine-containing polymer containing a carboxylic acid-type ion-exchange group and disposed on layer (I), wherein the water content of layer (I) is 26% or more and 35% or less: CF2—CF2??(1)Type: ApplicationFiled: November 6, 2019Publication date: February 10, 2022Applicant: ASAHI KASEI KABUSHIKI KAISHAInventors: Kenji NAKAGAWA, Masatsugu MORISHITA, Hideaki KURITA
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Publication number: 20210265973Abstract: The vibrator element includes at least one vibrating arm, and a weight provided to the vibrating arm, the weight is provided with at least one processing scar, when an axis which overlaps a center in a width direction of the vibrating arm, and which extends along an extending direction of the vibrating arm is a central axis, and an axis which overlaps a centroid of the vibrating arm, and which extends along the extending direction of the vibrating arm is a centroid axis, the processing scar is formed in at least an area at the centroid axis side with respect to the central axis, and S1>S2 an area of the processing scar located at the centroid axis side with respect to the central axis is S1, and an area of the processing scar located at an opposite side to the centroid axis with respect to the central axis is S2.Type: ApplicationFiled: February 18, 2021Publication date: August 26, 2021Inventor: Hideaki Kurita
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Publication number: 20210265975Abstract: The vibrator element includes a vibrating arm provided with an arm part, and a weight part which has a weight, the weight is provided with at least one processing scar, when an axis which overlaps a center in a width direction of the vibrating arm, and which extends along an extending direction of the vibrating arm is a central axis, and an axis which overlaps a centroid of the vibrating arm, and which extends along the extending direction of the vibrating arm is a centroid axis, the processing scar is formed in at least an area at an opposite side to the centroid axis, and S1<S2 an area of the processing scar located at the centroid axis side with respect to the central axis is S1, and an area of the processing scar located at an opposite side to the centroid axis with respect to the central axis is S2.Type: ApplicationFiled: February 18, 2021Publication date: August 26, 2021Inventor: Hideaki Kurita
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Publication number: 20200298350Abstract: An electronic device manufacturing method includes mounting an electronic component on a base, placing a lid on the base, and bringing a roller electrode to come into contact with the lid at a contact position overlapping a region where the base and the lid are welded inside an outer edge of the lid in a plan view, and bonding the lid to the base by seam welding.Type: ApplicationFiled: March 19, 2020Publication date: September 24, 2020Inventor: Hideaki KURITA
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Patent number: 9123883Abstract: A vibration device includes a semiconductor device, a first electrode and a second electrode located in a first surface of the semiconductor device, a vibration element, a third electrode and a fourth electrode located in a first surface of the vibration element, a first connection section that connects the first electrode and the third electrode, and a second connection section that connects the second electrode and the fourth electrode. The semiconductor device and the vibration element have mutually different thermal expansion coefficients. The vibration element has a coupling section located between the third electrode and the fourth electrode, and the coupling section has at least one bend section located between the third electrode and the fourth electrode.Type: GrantFiled: March 25, 2013Date of Patent: September 1, 2015Assignee: SEIKO EPSON CORPORATIONInventor: Hideaki Kurita
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Publication number: 20130249351Abstract: A vibration device includes a semiconductor device, a first electrode and a second electrode located in a first surface of the semiconductor device, a vibration element, a third electrode and a fourth electrode located in a first surface of the vibration element, a first connection section that connects the first electrode and the third electrode, and a second connection section that connects the second electrode and the fourth electrode. The semiconductor device and the vibration element have mutually different thermal expansion coefficients. The vibration element has a coupling section located between the third electrode and the fourth electrode, and the coupling section has at least one bend section located between the third electrode and the fourth electrode.Type: ApplicationFiled: March 25, 2013Publication date: September 26, 2013Applicant: SEIKO EPSON CORPORATIONInventor: Hideaki Kurita
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Patent number: 7777334Abstract: A semiconductor device comprising: a semiconductor layer including an element formation region, and first and second spaced apart isolation regions; an element in the element formation region; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad and having an opening which exposes part of the electrode pad; and a bump in the opening and covering part of the element when viewed from a top side, the bump including a first edge when viewed from the top side, the first isolation region being formed in a first region, the first region including a first specific distance outward from a first line directly below the first edge of the bump, the second isolation region being formed in a second region, the second region including a second specific distance inward from the first line.Type: GrantFiled: February 15, 2008Date of Patent: August 17, 2010Assignee: Seiko Epson CorporationInventors: Akinori Shindo, Masatoshi Tagaki, Hideaki Kurita
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Publication number: 20100092892Abstract: An object is to manufacture a substrate having a black matrix pattern with excellent ink repellency on the surface by an easy method. A fluorine-containing compound coated film in which 1 to 60 mm3 of an organic material layer containing 30 to 100% of a fluorine-containing compound is provided on a supporting film per 1 m2 of the supporting film and the organic material layer has a contact angle to xylene of 20 degrees or more is used.Type: ApplicationFiled: December 21, 2007Publication date: April 15, 2010Inventors: Hideaki Kurita, Hideki Matsuda
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Patent number: 7649260Abstract: A semiconductor device including: a semiconductor layer including an active region and an isolation region provided around the active region; an element formed in the active region; an interlayer dielectric formed above the semiconductor layer; and an electrode pad formed above the interlayer dielectric and having a rectangular planar shape having a short side and a long side, the electrode pad at least partially covering the element when viewed from a top side, and the semiconductor layer positioned in a specific range outward from a line extending vertically downward from the short side of the electrode pad being a forbidden region.Type: GrantFiled: June 19, 2006Date of Patent: January 19, 2010Assignee: Seiko Epson CorporationInventors: Akinori Shindo, Masatoshi Tagaki, Hideaki Kurita
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Patent number: 7598569Abstract: A semiconductor device including: a semiconductor layer; a transistor formed in the semiconductor layer and including a gate insulating layer and a gate electrode, the transistor being a high voltage transistor in which an insulating layer having a thickness greater than the thickness of the gate insulating layer is formed under an end portion of the gate electrode; an interlayer dielectric formed above the transistor; and an electrode pad formed above the interlayer dielectric and positioned over at least part of the gate electrode when viewed from a top side.Type: GrantFiled: May 5, 2006Date of Patent: October 6, 2009Assignee: Seiko Epson CorporationInventors: Akinori Shindo, Masatoshi Tagaki, Hideaki Kurita
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Publication number: 20080142967Abstract: A semiconductor device including: a semiconductor layer including an element formation region including an element; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad and having an opening exposing at least part of the electrode pad; and a bump in the opening and covering at least part of the element, the bump including first and second edges, the semiconductor layer having a forbidden region including: a first specific distance outward from a first line directly below the first edge, a second specific distance inward from the first line, a third specific distance outward from a second line directly below the second edge, and a fourth specific distance inward from the second line.Type: ApplicationFiled: February 15, 2008Publication date: June 19, 2008Inventors: Akinori Shindo, Masatoshi Tagaki, Hideaki Kurita
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Publication number: 20080142905Abstract: A semiconductor device including: a semiconductor layer including an element formation region including an element; a dielectric layer above the semiconductor; an electrode pad above the dielectric; a passivation layer above the pad and having an opening exposing part of the pad; and a bump in the opening and covering part of the element, the bump including first, second, third and fourth edges, the semiconductor having a forbidden region including: a first distance outward from a first line below the first edge, a second distance inward from the first line, a third distance outward from a second line below the second edge, a fourth distance inward from the second line, a fifth distance outward from a third line below the third edge, a sixth distance inward from the third line, a seventh distance outward from a fourth line below the fourth edge, and an eighth distance inward from the fourth line.Type: ApplicationFiled: February 15, 2008Publication date: June 19, 2008Inventors: Akinori Shindo, Masatoshi Tagaki, Hideaki Kurita
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Publication number: 20080142906Abstract: A semiconductor device comprising: a semiconductor layer including an element formation region, and first and second spaced apart isolation regions; an element in the element formation region; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad and having an opening which exposes part of the electrode pad; and a bump in the opening and covering part of the element when viewed from a top side, the bump including a first edge when viewed from the top side, the first isolation region being formed in a first region, the first region including a first specific distance outward from a first line directly below the first edge of the bump, the second isolation region being formed in a second region, the second region including a second specific distance inward from the first line.Type: ApplicationFiled: February 15, 2008Publication date: June 19, 2008Inventors: Akinori Shindo, Masatoshi Tagaki, Hideaki Kurita
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Publication number: 20070007662Abstract: A semiconductor device including: a semiconductor layer including an element formation region and an isolation region provided around the element formation region; an element formed in the element formation region; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric; a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; and a bump formed in the opening and having a rectangular planar shape having a short side and a long side, the bump at least partially covering the element when viewed from a top side, and the semiconductor layer positioned within a specific range inward and outward from a line extending vertically downward from the short side of the bump being a forbidden region.Type: ApplicationFiled: June 29, 2006Publication date: January 11, 2007Inventors: Akinori Shindo, Masatoshi Tagaki, Hideaki Kurita
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Publication number: 20070007599Abstract: A semiconductor device including: a semiconductor layer including an active region and an isolation region provided around the active region; an element formed in the active region; an interlayer dielectric formed above the semiconductor layer; and an electrode pad formed above the interlayer dielectric and having a rectangular planar shape having a short side and a long side, the electrode pad at least partially covering the element when viewed from a top side, and the semiconductor layer positioned in a specific range outward from a line extending vertically downward from the short side of the electrode pad being a forbidden region.Type: ApplicationFiled: June 19, 2006Publication date: January 11, 2007Applicant: Seiko Epson CorporationInventors: Akinori SHINDO, Masatoshi TAGAKI, Hideaki KURITA
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Publication number: 20060289961Abstract: A semiconductor device including: a semiconductor layer; a transistor formed in the semiconductor layer and including a gate insulating layer and a gate electrode, the transistor being a high voltage transistor in which an insulating layer having a thickness greater than the thickness of the gate insulating layer is formed under an end portion of the gate electrode; an interlayer dielectric formed above the transistor; and an electrode pad formed above the interlayer dielectric and positioned over at least part of the gate electrode when viewed from a top side.Type: ApplicationFiled: May 5, 2006Publication date: December 28, 2006Inventors: Akinori Shindo, Masatoshi Tagaki, Hideaki Kurita
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Patent number: 4665690Abstract: An internal combustion engine is provided in its exhaust system with a particulate filter for trapping combustible particulates contained in exhaust gas. A combustion promoting material injection device is provided for injecting a material for promoting combustion of the combustible particulates into the exhaust system upstream of the particulate filter. Further there are provided a bypass exhaust passage which bypasses the combustion promoting material injection device and the particulate filter, and a flow control valve which controls the amount of exhaust gas flowing through the bypass exhaust passage to control the amount of exhaust gas flowing into the particulate filter when said combustion promoting material is to be injected from the injecting device.Type: GrantFiled: January 10, 1986Date of Patent: May 19, 1987Assignee: Mazda Motor CorporationInventors: Yoshitaka Nomoto, Hirofumi Yamauchi, Shigeru Sakurai, Kenji Ohkubo, Hideaki Kurita, Kunihiro Yagi
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Patent number: 4119493Abstract: A peptide having the formulaX--A--B--Ywherein A and B are the same or different and represent an amino acid residue or a peptide residue; X represents an amino protective group and Y represents a carboxyl protective group, is prepared by reacting an amino acid or peptide having an N-terminal protective group or a salt thereof of the formula:X--A--OHwith an amino acid or peptide having a C-terminal protective group or a salt thereof of the formula:H--B--Yin the presence of metalloproteinase in an aqueous solution having a pH which maintains the enzyme activity of said metalloproteinase.Type: GrantFiled: June 3, 1977Date of Patent: October 10, 1978Assignee: (Zaidanhojin) Sagami Chemical Research CenterInventors: Yoshikazu Isowa, Muneki Ohmori, Hideaki Kurita, Tetsuya Ichikawa, Masanari Sato, Kaoru Mori
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Patent number: 4116768Abstract: A peptide having the formulaX--A--B--Ywherein A and B are the same or different and represent an amino acid residue or a peptide residue; X represents an amino protective group and Y represents a carboxyl protective group, is prepared by reacting an amino acid or peptide having an N-terminal protective group or a salt thereof of the formula:X--A--OHwith an amino acid or peptide having a C-terminal protective group or a salt thereof of the formula:H--B--Yin the presence of metalloproteinase in an aqueous solution having a pH which maintains the enzyme activity of said metalloproteinase.Type: GrantFiled: October 6, 1977Date of Patent: September 26, 1978Assignee: (Zaidanhojin) Sagami Chemical Research CenterInventors: Yoshikazu Isowa, Muneki Ohmori, Hideaki Kurita, Tetsuya Ichikawa, Masanari Sato, Kaoru Mori, Kiyotaka Oyama