Abstract: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

Abstract: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

Abstract: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

Abstract: A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region.

Abstract: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

Abstract: A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged with a first distance therebetween. The select gate line includes a first interconnection in the first direction, the first interconnection having a second line width larger than the first line width, and a second interconnection extending from an end portion of the first interconnection, the second interconnection having a third line width the same as the first line width. A first word-line adjacent to the select gate line is arranged having a second distance to the second interconnection, the second distance being (4N+1) times the first distance (N being an integer of 1 or more).

Abstract: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

Abstract: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

Abstract: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

Abstract: A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region.

Abstract: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

Abstract: In the semiconductor of the present invention, the first pair of pad lines consisting of a plurality of pads are arranged on the bottom portion of the recess portion of the enclosure, the recess portion being made at the center portion of the enclosure by the counterboring process to have a predetermined depth. At approximately center of the recess portion, a suction opening is made so as to suck the potting material from outside. In the recess portion of the enclosure, the semiconductor chip is supported. The semiconductor chip has the second pair of pad lines arranged to oppose to the first pair of pad lines and electrically connected to the first pair of pad lines respectively. The potting material is poured into the recess portion so as to completely cover the semiconductor chip. At the same time, the potting material is sucked from the suction opening.

Abstract: A reflective silver halide photographic light-sensitive material is disclosed. The light-sensitive material comprises a reflective support having thereon a silver halide emulsion layer wherein the support have an oxygen permeability of not more than 2.0 ml/m.sup.2 .multidot.hr.multidot.atm and the silver halide emulsion layer contains a magenta coupler represented by the following Formula I; ##STR1## wherein Ar is an aryl group; Y is a hydrogen atom or a substituent capable of splitting off upon reaction with the oxidation product of a color developing agent; X is a halogen atom, an alkoxy group or an alkyl group; R is a strait- or branched-chain alkyl group having 1 to 20 carbon atoms; J is a strait- or branched-chain alkylene group; and n is an integer of from 0 to 4, when n is 2 or more, the plurality of Xs may be the same or different. The light-sensitive material is excellent in red color reproducibility and light fastness of red colored images.

Abstract: A silver halide photographic emulsion containing silver halide grains having a silver chloride content of not less than 90 mol % and a method for preparing thereof are disclosed, wherein the silver halide grains are obtained by forming said silver halide grains in the presence of a water-soluble iridium compound and a nitrogen-containing heterocyclic compound capable of forming sparingly-soluble silver salt; and by controlling the addition of said iridium compound, whereby the photographic emulsion is improved in the dependence of gradation on exposure intensity.

Abstract: A light-sensitive silver halide photographic material which comprises a support and provided thereon a silver halide emulsion layer containing silver halide grains of which silver chloride content is not less than 90 mol %, and which have been formed in the presence of an iridium compound and a nitrogen containing heterocyclic compound, and under acidic condition is disclosed.