Abstract: According to one embodiment, a voltage-controlled oscillation (VCO) circuit includes a current source, an oscillation core unit, an amplitude detection unit, a current control unit, a low pass filter, and a switch. The current source supplies a bias current to the oscillation core unit in accordance with a current control signal. The oscillation core unit oscillates according to the bias current and outputs an oscillation signal. The amplitude detection unit outputs a detection voltage according to an amplitude of the oscillation signal. The current control unit outputs a control signal so that the detection voltage is equal to a reference voltage. The low pass filter generates the current control signal by filtering the control signal, and then supplies the current control signal to the current source. The switch is connected in parallel with the low pass filter.

Abstract: According to one embodiment, a voltage-controlled oscillation (VCO) circuit includes a current source, an oscillation core unit, an amplitude detection unit, a current control unit, a low pass filter, and a switch. The current source supplies a bias current to the oscillation core unit in accordance with a current control signal. The oscillation core unit oscillates according to the bias current and outputs an oscillation signal. The amplitude detection unit outputs a detection voltage according to an amplitude of the oscillation signal. The current control unit outputs a control signal so that the detection voltage is equal to a reference voltage. The low pass filter generates the current control signal by filtering the control signal, and then supplies the current control signal to the current source. The switch is connected in parallel with the low pass filter.

Abstract: A digital PLL circuit includes: an oscillation circuit, wherein an oscillation frequency is controlled by changing the number of capacitance elements to be connected in parallel to an inductance element; and a phase comparator part configured to perform a digital phase comparison of a reference clock and a delayed clock thereof, with an oscillation circuit output; and based on the comparison result, to control the number of the capacitance elements so as to bring the phase of the oscillation circuit output closer to the reference clock phase, wherein the capacitance element includes: a coarse adjustment capacitor configured to have a predetermined capacitance; and fine adjustment capacitors configured to have a capacitance of 1/n of that of the coarse adjustment capacitor, wherein a predetermined number of the fine adjustment capacitors function as one coarse adjustment capacitor at the time of coarse adjustment.

Abstract: A digital PLL circuit includes: an oscillation circuit, wherein an oscillation frequency is controlled by changing the number of capacitance elements to be connected in parallel to an inductance element; and a phase comparator part configured to perform a digital phase comparison of a reference clock and a delayed clock thereof, with an oscillation circuit output; and based on the comparison result, to control the number of the capacitance elements so as to bring the phase of the oscillation circuit output closer to the reference clock phase, wherein the capacitance element includes: a coarse adjustment capacitor configured to have a predetermined capacitance; and fine adjustment capacitors configured to have a capacitance of 1/n of that of the coarse adjustment capacitor, wherein a predetermined number of the fine adjustment capacitors function as one coarse adjustment capacitor at the time of coarse adjustment.

Abstract: A first differential amplifier includes first and second transistors. A bias circuit includes a second differential amplifier, a constant-current source, and a capacitor. The bases of third and fourth transistors constituting a second differential amplifier, are connected to those of the first and second transistors, respectively. The constant-current source supplies a constant current to the third and fourth transistors, and one end of the capacitor is connected to a connection node of the constant-current source and fourth transistor. In the bias circuit, when a high-level signal is supplied to the base of the first transistor, the capacitor is charged and discharged in accordance with the operations of the third and fourth transistors, with the result that the base potential of the first and second transistors is stabilized, and the operation current flowing through the first differential amplifier is prevented from increasing.

Abstract: An output circuit comprising a differential amplifier circuit for providing a pair of complementary output signals corresponding to an input signal supplied to first and second signal input terminals thereof, an output transistor having a base connected to one output node of the differential amplifier circuit, a collector connected to a first power source potential supply terminal, and an emitter connected to a signal output terminal, a current mirror circuit having a current input terminal connected to a current source and a current output terminal connected to the signal output terminal, and a capacitor connected between the other output node of the differential amplifier circuit and the current input terminal of the current mirror circuit.

Abstract: A logic circuit includes first and second NPN bipolar transistors whose collector-emitter paths are serially connected between a power source potential terminal and a ground terminal, the connection node of the first and second bipolar transistors being connected to a signal input terminal; a first CMOS logic circuit having an input terminal connected to a signal input terminal and an output terminal connected to the base of the first NPN bipolar transistor; a second CMOS logic circuit having an input terminal connected to the signal input terminal and an output terminal connected to the signal output terminal; a first switching circuit connected between the signal output terminal and the base of the second bipolar transistor, and to be set OFF when an input signal is set at a level at which the first NPN bipolar transistor is rendered conductive, and to be set ON when the input signal is set at a level at which the first NPN bipolar transistor is rendered nonconductive; and a second switching circuit connect

Abstract: A logic circuit comprises a current control means including first and second MOS transistors for controlling the current to the output circuit and also for controlling the output wave form, in accordance with the input signal and the output signal. When the output signal rises from a low level to a high level, a large current is supplied to the output circuit to get a steep rise. When the output signal is high level, the current to the output circuit becomes small, and the power consumption is reduced.