Patents by Inventor Hideaki Matsuyama

Hideaki Matsuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240109332
    Abstract: A recording apparatus includes a conveyance unit that conveys a recording medium in a first direction toward a recording head for ejecting a liquid, a tank including a containing chamber containing the liquid to be supplied to the recording head, and an injection port through which the liquid is injected into the containing chamber, the tank being disposed downstream of the conveyance unit in the first direction, a rotatable lever that holds a tank cap for closing the injection port, and a cover that rotates about a rotation shaft between an open position for exposing the lever and a closed position for covering the lever, the rotation shaft being disposed upstream of the conveyance unit in the first direction. The cover includes a sliding portion that is provided on a surface facing the lever and comes into contact with the lever while the cover is rotating toward the closed position.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 4, 2024
    Inventors: Taiji Maruyama, Koya Iwakura, Hideaki Matsumura, Tetsu Hamano, Nobuhiro Toki, Daiju Takeda, Fumie Kameyama, Koki Shimada, Shota Asada, Ken Takenaga, Yusuke Tanaka, Yuta Araki, Atsushi Matsuyama, Yusuke Naratani, Kousuke Tanaka
  • Patent number: 11932021
    Abstract: A recording apparatus includes a tank including a chamber configured to store liquid to be supplied to a recording head that ejects the liquid and a filling port from which the liquid is injected into the chamber, and an injection auxiliary member configured to assist injecting of the liquid into the chamber from the filling port, the injection auxiliary member including a first and a second flow channels each defined by a first or a second upper end portion that opens toward outside of the tank and a first or a second lower end portion that opens toward inside of the tank, wherein the second flow channel has an expansion portion arranged in a middle portion between the second upper end portion and the second lower end portion and configured to form a step to expand a cross-sectional area.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: March 19, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yusuke Naratani, Koya Iwakura, Hideaki Matsumura, Tetsu Hamano, Nobuhiro Toki, Daiju Takeda, Fumie Kameyama, Koki Shimada, Shota Asada, Ken Takenaga, Yusuke Tanaka, Yuta Araki, Taiji Maruyama, Atsushi Matsuyama, Kousuke Tanaka, Toshimitsu Takahashi, Nanae Uchinuno
  • Patent number: 11862687
    Abstract: A nitride semiconductor device is provided, comprising: a first nitride semiconductor layer of a first conductivity-type; a second nitride semiconductor layer of a second conductivity-type provided above the first nitride semiconductor layer; a junction region of a first conductivity-type which is provided to extend in a direction from a front surface of the second nitride semiconductor layer to the first nitride semiconductor layer and has a doping concentration NJFET equal to or higher than that of the first nitride semiconductor layer; and a source region of a first conductivity-type which is provided more shallowly than the junction region and has a doping concentration equal to or higher than the doping concentration NJFET, wherein a dopant of the source region is an element with an atomic weight larger than that of a dopant in the junction region.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: January 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryo Tanaka, Shinya Takashima, Hideaki Matsuyama, Katsunori Ueno, Masaharu Edo
  • Patent number: 11257676
    Abstract: A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 22, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hideaki Matsuyama, Shinya Takashima, Katsunori Ueno, Ryo Tanaka, Masaharu Edo, Daisuke Mori, Hirotaka Suda, Hideaki Teranishi, Chizuru Inoue
  • Publication number: 20210104607
    Abstract: A nitride semiconductor device is provided, comprising: a first nitride semiconductor layer of a first conductivity-type; a second nitride semiconductor layer of a second conductivity-type provided above the first nitride semiconductor layer; a junction region of a first conductivity-type which is provided to extend in a direction from a front surface of the second nitride semiconductor layer to the first nitride semiconductor layer and has a doping concentration NJFET equal to or higher than that of the first nitride semiconductor layer; and a source region of a first conductivity-type which is provided more shallowly than the junction region and has a doping concentration equal to or higher than the doping concentration NJFET, wherein a dopant of the source region is an element with an atomic weight larger than that of a dopant in the junction region.
    Type: Application
    Filed: August 24, 2020
    Publication date: April 8, 2021
    Inventors: Ryo TANAKA, Shinya TAKASHIMA, Hideaki MATSUYAMA, Katsunori UENO, Masaharu EDO
  • Publication number: 20200411647
    Abstract: A nitride semiconductor device includes a transistor having a channel region in a gallium nitride-based semiconductor layer. The transistor includes: a gate insulating film provided above the gallium nitride-based semiconductor layer; an intermediate layer arranged between the gallium nitride-based semiconductor layer and the gate insulating film, having a band gap smaller than that of the gate insulating film, and having a band offset with the gallium nitride-based semiconductor layer; a gate electrode provided on the gate insulating film; a first conductivity type source region provided in the gallium nitride-based semiconductor layer; and a source electrode provided on the gallium nitride-based semiconductor layer and being in contact with the source region. The intermediate layer is arranged at a position opposed to the gate electrode through the gate insulating film and avoids a source contact region in which the source electrode is in contact with the source region.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 31, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hideaki MATSUYAMA, Katsunori UENO, Shinya TAKASHIMA, Ryo TANAKA, Yuta FUKUSHIMA
  • Patent number: 10181514
    Abstract: In a case where a semiconductor layer is epitaxially grown on a step shape formed due to CBL (current blocking layer) formation, the crystallinity of the semiconductor layer lowers. Also, a GaN layer that is epitaxially regrown on the CBL is not formed continuously by epitaxial growth, and therefore the crystallinity of the GaN layer lowers. A vertical semiconductor device manufacturing method is provided that comprises: a step of epitaxially growing a gallium nitride-based n-type semiconductor layer on a gallium nitride-based semiconductor substrate; a step of epitaxially growing a gallium nitride-based p-type semiconductor layer on the n-type semiconductor layer; and a step of ion-implanting p-type impurities to form a p+-type embedded region selectively in a predetermined depth range across the boundary between the n-type semiconductor layer and the p-type semiconductor layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hideaki Matsuyama, Shinya Takashima, Katsunori Ueno, Takuro Inamoto, Masaharu Edo
  • Publication number: 20190006184
    Abstract: A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 3, 2019
    Inventors: Hideaki MATSUYAMA, Shinya TAKASHIMA, Katsunori UENO, Ryo TANAKA, Masaharu EDO, Daisuke MORI, Hirotaka SUDA, Hideaki TERANISHI, Chizuru INOUE
  • Patent number: 9947537
    Abstract: There is a problem that even if impurities are made to thermally diffuse in a temperature range of 700° C.-1150° C., a good ohmic contact cannot be formed in a p-type group-III nitride semiconductor layer. Provided is a semiconductor device manufacturing method having a group-III nitride semiconductor substrate and a p-type group-III nitride semiconductor layer on the group-III nitride semiconductor substrate, including forming a magnesium containing layer on and in direct contact with the p-type group-III nitride semiconductor layer; and annealing the p-type group-III nitride semiconductor layer at a temperature more than or equal to 1300° C. to form a p+-type region which contains magnesium as an impurity in the p-type group-III nitride semiconductor layer located immediately below the magnesium containing layer.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 17, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hideaki Matsuyama
  • Publication number: 20180097063
    Abstract: In a case where a semiconductor layer is epitaxially grown on a step shape formed due to CBL (current blocking layer) formation, the crystallinity of the semiconductor layer lowers. Also, a GaN layer that is epitaxially regrown on the CBL is not formed continuously by epitaxial growth, and therefore the crystallinity of the GaN layer lowers. A vertical semiconductor device manufacturing method is provided that comprises: a step of epitaxially growing a gallium nitride-based n-type semiconductor layer on a gallium nitride-based semiconductor substrate; a step of epitaxially growing a gallium nitride-based p-type semiconductor layer on the n-type semiconductor layer; and a step of ion-implanting p-type impurities to form a p+-type embedded region selectively in a predetermined depth range across the boundary between the n-type semiconductor layer and the p-type semiconductor layer.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 5, 2018
    Inventors: Hideaki MATSUYAMA, Shinya TAKASHIMA, Katsunori UENO, Takuro INAMOTO, Masaharu EDO
  • Publication number: 20180019129
    Abstract: There is a problem that even if impurities are made to thermally diffuse in a temperature range of 700° C.-1150° C., a good ohmic contact cannot be formed in a p-type group-III nitride semiconductor layer. Provided is a semiconductor device manufacturing method having a group-III nitride semiconductor substrate and a p-type group-III nitride semiconductor layer on the group-III nitride semiconductor substrate, including forming a magnesium containing layer on and in direct contact with the p-type group-III nitride semiconductor layer; and annealing the p-type group-III nitride semiconductor layer at a temperature more than or equal to 1300° C. to form a p+-type region which contains magnesium as an impurity in the p-type group-III nitride semiconductor layer located immediately below the magnesium containing layer.
    Type: Application
    Filed: May 31, 2017
    Publication date: January 18, 2018
    Inventor: Hideaki MATSUYAMA
  • Patent number: 8586484
    Abstract: A film forming process is performed on a substrate in a deposition chamber. A first electrode is provided in the deposition chamber and is grounded. A second electrode is provided in the deposition chamber to face the first electrode. A radio frequency power supply supplies radio frequency power to the second electrode. A DC power supply supplies a DC bias voltage to the second electrode. A control unit adjusts a bias voltage to be less than the potential of the second electrode when the radio frequency power is supplied, but the bias voltage is not supplied. In this way, it is possible to improve film quality while preventing a reduction in the deposition rate of a film during deposition.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: November 19, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hideaki Matsuyama, Takehito Wada
  • Publication number: 20120115257
    Abstract: A film forming process is performed on a substrate in a deposition chamber. A first electrode is provided in the deposition chamber and is grounded. A second electrode is provided in the deposition chamber to face the first electrode. A radio frequency power supply supplies radio frequency power to the second electrode. A DC power supply supplies a DC bias voltage to the second electrode. A control unit adjusts a bias voltage to be less than the potential of the second electrode when the radio frequency power is supplied, but the bias voltage is not supplied. In this way, it is possible to improve film quality while preventing a reduction in the deposition rate of a film during deposition.
    Type: Application
    Filed: December 16, 2009
    Publication date: May 10, 2012
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hideaki Matsuyama, Takehito Wada
  • Publication number: 20050031797
    Abstract: A method and an apparatus for forming a hard film, such as a hard carbon film, using only ions in a plasma. A shielding member in the form of a magnet is disposed between a plasma source and a substrate. A plasma CVD method is applied for decomposing a raw material in the plasma. The film is formed from the decomposed material.
    Type: Application
    Filed: June 29, 2004
    Publication date: February 10, 2005
    Inventor: Hideaki Matsuyama
  • Publication number: 20050031907
    Abstract: A magnetic recording medium that is resistant to the spin-off phenomenon caused by high speed rotation is disclosed. The medium has a thin lubricating layer suitable for higher recording density. A manufacturing method for making the magnetic recording medium also is disclosed. The magnetic recording medium is successively laminated with at least a magnetic film, protective film, and lubricating layer on a non-magnetic substrate. The lubricating layer is an average of one molecule or less in thickness and 90% or more of the area of the lubricating layer is not chemically adsorbed to the protective film. Fluorine termination of the protective-film surface prevents the chemical adsorption of lubricant, preventing the formation of a bonded lubricating layer and leaving behind a mobile lubricating layer of approximately one molecule in thickness that is not spun off. The resistance to spin-off is due to the fact that the protective-film surface and the lubricant both consist of carbon fluoride.
    Type: Application
    Filed: June 25, 2004
    Publication date: February 10, 2005
    Inventor: Hideaki Matsuyama
  • Publication number: 20010031382
    Abstract: A carbon protective film of a magnetic recording medium includes a surface region having a high nitrogen concentration. The nitrogen-doped surface region enhances surface energy and improves wettability of the protective film with a liquid lubricant. The nitrogen is implanted by plasma treatment to produce a surface region in the protective film that includes from 6 to 20 at % of nitrogen in the surface region within 30 Å from the film surface. The treatment reduces the contact angle of the film surface with water to the range from of 10 to 30 degrees.
    Type: Application
    Filed: January 10, 2001
    Publication date: October 18, 2001
    Inventors: Kazuhiro Kusakawa, Michinari Kamiyama, Masaki Miyazato, Masanori Yoshihara, Hideki Matsuo, Hideaki Matsuyama
  • Patent number: 5162960
    Abstract: The formation of a gap in a magnetic head core or the junction of a thin magnetic film of a metal with an oxide substrate of a magnetic head made of a composite of a thin magnetic film of a metal with an oxide material are conducted by the thermal diffusion between gold layers themselves at a low temperature. Then, chromium or titanium is provided between the gold layer and the junction surface to prevent deterioration of magnetic characteristics and generation of a false gap and, at the same time, to heighten the junction strength. The thermal diffusion between the gold layers themselves is effected at a temperature lower than that of glass fusion to suppress the deterioration of magnetic characteristics, distortion caused by thermal expansion, and diffusion reaction on the interface. The chromium or titanium layer works to maintain function strength between the thin magnetic layer or the oxide substrate and the gold layer.
    Type: Grant
    Filed: November 20, 1990
    Date of Patent: November 10, 1992
    Assignee: Sony Corporation
    Inventors: Katsumi Sakata, Ikuko Sato, Tatsuo Kumura, Toshito Ikeda, Hiroya Eguchi, Hideaki Matsuyama, Hideaki Karamon
  • Patent number: 5133814
    Abstract: A novel soft magnetic amorphous alloy thin film which, on account of the composition of the film consisting in a combination of a transition metal, a metalloid or semiconducting element, namely B, C or Si and an oxide derived from the starting material, is endowed with a comminuted and dispersed structure of a magnetic amorphous phase and a nonmagnetic amorphous phase. The soft magnetic amorphous alloy thin film may be applied to a magnetic head for short wavelength recording which is required to cope with high frequency characteristics and high coercivity of the recording medium.
    Type: Grant
    Filed: September 17, 1990
    Date of Patent: July 28, 1992
    Assignee: Sony Corporation
    Inventors: Hideaki Matsuyama, Hideaki Karamon