Patents by Inventor Hideaki Nabekura

Hideaki Nabekura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9748202
    Abstract: A semiconductor device includes a first circuit board having a first chip and a second chip mounted on a first base, the second chip having a greater height from the first base than that of the first chip; and a second circuit board having a third chip and a fourth chip mounted on a second base, the fourth chip having a greater height from the second base than that of the third chip, the second circuit board being disposed overlapping with the first base such that the second base faces the first chip, and the second base not contacting the second chip.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: August 29, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Hideaki Nabekura
  • Publication number: 20170018528
    Abstract: A semiconductor device includes a first circuit board having a first chip and a second chip mounted on a first base, the second chip having a greater height from the first base than that of the first chip; and a second circuit board having a third chip and a fourth chip mounted on a second base, the fourth chip having a greater height from the second base than that of the third chip, the second circuit board being disposed overlapping with the first base such that the second base faces the first chip, and the second base not contacting the second chip.
    Type: Application
    Filed: June 22, 2016
    Publication date: January 19, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Hideaki NABEKURA
  • Patent number: 5530815
    Abstract: Asynchronous computation commands sent from a command control are held in a command queue. The executable command is selected and supplied to a pipelined asynchronous computing unit. A status area is assured for each command held in the command queue and pipeline bits indicative of a progressing state of the execution of the command in the asynchronous computing unit are stored. A queue verifier discriminates the pipeline bits and verifies that a plurality of pipeline stages does not exist in the status area of the same command and that a plurality of pipeline stages does not exist among the commands, thereby guaranteeing the correct order and operation of the execution of the commands.
    Type: Grant
    Filed: August 12, 1993
    Date of Patent: June 25, 1996
    Assignee: Fujitsu Limited
    Inventors: Hideaki Nabekura, Shuntaro Fujioka