Abstract: An automatic circuit design apparatus includes an analyzer (11) for analyzing a file in a form of a table, in which both connection conditions concerning a plurality of circuit components (e.g., intellectual properties) within an integrated circuit and connections among the plurality of circuit components corresponding to the connection conditions are described, and a description creating unit (12) for creating a description of the integrated circuit according to HDL based on analytical results from the analyzer (11).

Abstract: In a semiconductor integrated circuit having a gate array structure, within a cell, isolation transistors are disposed in series between an intra-cell gate output terminal and an intra-cell power supply wiring section, or between the intra-cell gate output terminal and an intra-cell ground wiring section. Isolation transistors are disposed in series between an extra-cell gate output terminal and an extra-cell power supply wiring section between cells, or between the extra-cell gate output terminal and an extra-cell ground wiring section.

Abstract: In the semiconductor integrated circuit of a gate array structure, within a cell, a plurality of isolation transistors are disposed in series between an intra-cell gate output terminal and an intra-cell power supply wiring section, or between the intra-cell gate output terminal and an intra-cell ground wiring section. While between cells, a plurality of isolation transistors are disposed in series between an extra-cell gate output terminal and an extra-cell power supply wiring section, or between the extra-cell gate output terminal and an extra-cell ground wiring section.

Abstract: A circuit for suppressing period jitter of the clock output of a ring oscillator caused by supply voltage fluctuations. The ring oscillator includes n identical current controlled delay circuits 26.1-n connected in a ring, and a replica circuit 36 identical to the current controlled delay circuit. The replica circuit 36 receives a constant input voltage so that its output is always at a high level. A differential amplifier 35 receiving a reference potential Vref is connected in a negative feedback circuit with replica circuit 36, so that the output of the replica circuit 36 is held equal to the reference potential Vref. An output of the negative feedback circuit is also applied to each of the current controlled delay circuits 26.1-n, so that their high level outputs are held equal to the reference potential Vref.