Patents by Inventor Hideaki Nakura

Hideaki Nakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6127720
    Abstract: A semiconductor device provided with a wide and shallow first groove and a second groove in the first groove area, having a narrower width than that of the first groove around a predetermined area in a one-conductive area provided in the upper region of a semiconductor substrate as a mesa groove, wherein at least the second groove is covered with an electrical insulator. The upper surface of the electrical insulator is located approximately as high as or lower than the upper surface of the electrical insulating film. Thus, especially in a mesa semiconductor device with a high-voltage resistance, an insulating protective layer having a sufficient thickness can be formed stably over the entire region of a mesa groove. As a result, the variation in high-voltage resistance characteristics can be decreased and the processing yield affected by breakage or cracking in the mesa groove region during subsequent processes caused by the formation of the mesa groove can be improved greatly.
    Type: Grant
    Filed: May 11, 1998
    Date of Patent: October 3, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Hideaki Nakura, Isamu Kawashima, Jutarou Kotani, Hidekazu Nakamura
  • Patent number: 5629551
    Abstract: A semiconductor device includes on a semiconductor substrate an output transistor which is composed of a collector region, a first base region and a first emitter region, and a temperature detection transistor composed of the collector region, a second base region and a second emitter region. The output transistor is provided at a center of the collector region of the semiconductor substrate. A vacant region is formed on a center of the output transistor, and the temperature detection transistor is provided in the vacant region.
    Type: Grant
    Filed: July 18, 1995
    Date of Patent: May 13, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Nakura, Masami Yokozawa, Kazuhiko Tsubaki, Masasuke Yoshimura
  • Patent number: 5461252
    Abstract: A semiconductor device includes on a semiconductor substrate an output transistor which is composed of a collector region, a first base region and a first emitter region, and a temperature detection transistor composed of the collector region, a second base region and a second emitter region. The output transistor is provided at a center of the collector region of the semiconductor substrate. A vacant region is formed on a center of the output transistor, and the temperature detection transistor is provided in the vacant region.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: October 24, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Nakura, Masami Yokozawa, Kazuhiko Tsubaki, Masasuke Yoshimura
  • Patent number: 5298793
    Abstract: There is disclosed a semiconductor device having an electrode for wire bonding, comprising a first aluminum layer, a nickel-aluminum alloy layer, and a second aluminum layer. The electrode is suitable for bonding with copper wire, since the electrode withstands a wide range of bonding conditions--mechanical pressure, ultrasonic wave power and such, and permits a reliable electrical connection to be maintained.
    Type: Grant
    Filed: August 13, 1992
    Date of Patent: March 29, 1994
    Assignee: Matsushita Electronics Corporation
    Inventors: Jutaro Kotani, Masahiro Ihara, Hideaki Nakura, Masami Yokozawa