Abstract: A digital signal receiver is structured to receive and demodulate a digital signal. Such digital signal may comprise, for example, a television signal of character multiplex transmission having a digital signal included in the vertical blanking period of the television signal and a digital signal receiver may be structured to reproduce the digital signal from the television signal. The digital signal includes a clock run-in signal (CRI), a framing code signal (FRC) and a bit serial data signal (DA) disposed in succession. An error of the framing code or the data signal caused by a low frequency region group delay characteristic of a transmission path between the transmission and the demodulation is detected based on the digital signal. Upon detection of an error, a waveform distortion of the framing code signal and the data signal is corrected by means of a correcting circuit (15) such as an LC circuit, whereby an error of the data signal to be demodulated thereafter is prevented.

Abstract: A digital signal receiver is structured to receive and demodulate a digital signal. Such digital signal may comprise, for example, a television signal of character multiplex transmission having a digital signal included in the vertical blanking period of the television signal and a digital signal receiver may be structured to reproduce the digital signal from the television signal. The digital signal includes a clock run-in signal (CRI), a framing code signal (FRC) and a bit serial data signal (DA) disposed in succession. An error of the framing code or the data signal caused by a low frequency region group delay characteristic of a transmission path between the transmission and the demodulation is detected based on the digital signal. Upon detection of an error, a waveform distortion of the framing code signal and the data signal is corrected by means of a correcting circuit (15) such as an LC circuit, whereby an error of the data signal to be demodulated thereafter is prevented.

Abstract: A switching regulated power supply apparatus, comprising: an alternative current power source, a first rectifier for rectifying the alternate current output, a high frequency reference pulse generator, a pulse width modulator for modulating the pulse width of the reference pulse output as a function of a control signal, a switching transistor for on/off controlling the output from the first rectifier as a function of the pulse width modulated output, a high frequency transformer connected in series with the first rectifier and the switching transistor, a second rectifier for rectifying the output from the high frequency transformer, and a smoothing circuit for smoothing the output from the second rectifier, the output from the smoothing circuit being applied to the pulse width modulator as a control signal, characterized in that the said apparatus further comprises a resonance capacitor coupled to the said high frequency transformer for causing resonance cooperatively with the said high frequency transformer