Abstract: A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.

Abstract: A semiconductor device comprising: a first-conductivity-type base layer; a second-conductivity-type emitter layer formed on a first main surface of said first-conductivity-type base layer; a collector electrode formed in contact with a surface of said second-conductivity-type emitter layer; a second-conductivity-type base layer formed on a second main surface of said first-conductivity-type base layer; a plurality of trenches which extend through said second-conductivity-type base layer to reach a predetermined depth of said first-conductivity-type base layer, and has a longitudinal direction in one direction; a gate electrode formed in said trench via a gate insulating film; a first-conductivity-type emitter layer selectively formed in contact with side walls of said trench, in a surface portion of said second-conductivity-type base layer; an emitter electrode formed in contact with a surface of said second-conductivity-type base layer and a surface of said first-conductivity-type emitter layer; and a second

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: It is an object of the present invention to provide a high-frequency module whose production yield as a complete module can be prevented from being lowered. The high-frequency module according to the present invention includes a main module including a first high-frequency circuit at least a part of which is constituted by a conductive pattern built in a multi-layered substrate and a sub-module including a second high-frequency circuit, and the sub-module is inserted into a cavity formed in the main module. According to the present invention, the main module including the first high-frequency circuit and the sub-module including the second high-frequency circuit are constituted as separate components and the main module and the sub-module are integrated by inserting the sub-module into the cavity formed in the main module. Therefore, it is possible to use only a main module and sub-module that have been inspected after manufacture and found to be non-defective.

Abstract: An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate so as to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate located outside the isolating structure, a plurality of cell structures defined in the device region and divided in segments by insulated trench-shaped gates so as to have a base region covered with an emitter region in its upper surface, a collector region, and an emitter electrode electrically connected to the emitter region and the base region, a dummy base region contiguous to the cell structures and configured as a base region that has its upper surface left without the emitter region connected to the emitter electrode, and a connection part to electrically connect the peripheral diffusion region to the emitter electrode.

Abstract: A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and t

Abstract: The present invention provides a substrate holding method capable of contributing to improvement in performance of an electronic part. A plastic film is adhered to a holding frame by using an adhesive tape having a proper gas releasing characteristic such that total quantity of gas detected when analysis using gas chromatograph mass spectrometry (dynamic HS-GC-MS) is conducted under test conditions of 180° C. and 10 minutes is 100.5 ?g/g or less in n-tetradecane. In the case where the plastic film held by the holding frame is subjected to a process of manufacturing an electronic part (for example, a solar battery), even when a process accompanying generation of heat during the manufacturing process (for example, a film forming process such as plasma CVD) is performed on the plastic film, a release amount of unnecessary gas released from the adhesive tape due to the influence of the heat is suppressed, so that deterioration in the performance of the electronic part caused by the unnecessary gas is suppressed.

Abstract: An object of the invention is to connect different dielectrics electrically to each other in the direction of main surface of a sheet in a multilayer ceramic substrate and to increase the degree of flexibility in design and make the multilayer ceramic substrate compact in size. A multilayer ceramic substrate in accordance with the invention is formed of a plurality of laminated ceramic substrates including such a composite ceramic substrate of different materials that is made by inserting the second ceramic substrate in a pounched-out portion made in the first ceramic substrate and by planarizing its top and bottom surfaces, wherein a conductive layer is formed in a portion across a boundary between the first ceramic substrate and the second ceramic substrate of the interface of the composite ceramic substrate of different materials.

Abstract: A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.

Abstract: A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are e

Abstract: A vertical semiconductor device including a first conductivity type base layer having resistance higher then of a first conductivity type buffer layer, the first conductivity type buffer layer formed in one surface portion of the first conductivity type base layer, a second conductivity type drain layer selectively formed in a surface portion of the first conductivity type buffer layer, a second conductivity type base layer selectively formed in the other surface portion of the first conductivity type base layer, a first conductivity type source layer selectively formed in a surface portion of the second conductivity type base layer, a gate insulating film formed on the second conductivity type base layer between the first conductivity type source layer and the first conductivity type base layer, a gate electrode formed on the second conductivity type base layer via the gate insulating film, a drain electrode electrically connected to the second conductivity type drain layer, and a source electrode electrical

Abstract: A semiconductor device includes: a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a well layer of a second conductivity type formed on the barrier layer; a trench formed from the surface of the well layer to such a depth as to reach a region in the vicinity of a junction surface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of the second conductivity type selectively formed in a surface portion of the well layer, a source layer of the first conductivity type selectively formed in the surface portion of the well layer so as to contact a side wall of the gate insulating film in the trench and the contact layer, and a first main electrode formed so as to contact the contact layer and the source layer, wherein assuming that a total sum of impurity densities in the region of the barrier layer between the trenches is Qn, the Qn has a relation of the following equation: Q

Abstract: A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.

Abstract: A frame-shaped holding frame which has a small thermal expansion coefficient is used. When a complex member in which a metal material is impregnated in a ceramic material, which has a smaller thermal expansion coefficient than 10 ppm/° C., is used, a warp and a wrinkle are greatly decreased. In particular, in the case of a material with a thermal expansion coefficient of 6.5 ppm/° C. or smaller, the warp and the wrinkle are not caused. When the flexible substrate is adhered to the holding frame by an adhesive, an adhesion area may be obtained so that a sufficient strength is kept. Also, since the flexible substrate is adhered onto the upper surface of the holding frame, the thickness of the holding frame is independent on fixing of the substrate. The thickness may be set so that a mechanical strength is kept and the substrate is smoothly transferred.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: In a trench MOS gate structure of a semiconductor device where trenches (T) are located between an n-type base layer (1) and an n-type source layer (3), a p-type channel layer (12) is formed adjacent to side walls of the trenches, having an even concentration distribution along a depthwise dimension of the trenches. The p-type channel layer enables saturation current to decrease without a raise of ON-resistance of the device, and resultantly a durability against short-circuit can be enhanced. The n-type source layer formed adjacent to the side walls of the trench also further enhances the durability against short-circuit. Providing contacts of the emitter electrode (7) with the n-type source layer at the side walls of the trenches permits a miniaturization of the device and a reduction of the ON-resistance as well.

Abstract: It is an object of the present invention to provide a high-frequency module whose production yield as a complete module can be prevented from being lowered.

Abstract: An IGBT has a p-emitter layer and p-base layer, which are arranged on both sides of an n-base layer. A pair of main trenches are formed to extend through the p-base layer and reach the n-base layer. In a current path region interposed between the main trenches, a pair of n-emitter layers are formed on the surface of the p-base layer. A narrowing trench is formed to extend through the p-base layer and reach the n-base layer. The narrowing trench narrows a hole flow path formed from the n-base layer to the emitter electrode through the p-base layer, thereby increasing the hole current resistance.

Abstract: This invention provides a multilayer ceramic substrate which has a consistent quality, and which has with no swelling or collapse in the inner periphery of the cavity, wherein the bottom of the cavity is flat to enable stable packaging of the desired device at a high precision, and wherein L and C can be formed by the internal conductor at a high precision; and a method for producing a multilayer ceramic substrate and an apparatus therefor by which a multilayer ceramic substrate can be readily produced in a simple procedure by using an apparatus of simple structure.