Patents by Inventor Hideaki Nonami

Hideaki Nonami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8018006
    Abstract: A semiconductor device includes a lower substrate, a thin semiconductor layer and an insulating layer formed between the lower substrate and the semiconductor layer. An active transistor area is formed with a base formed along a surface of the semiconductor layer, an emitter region formed in the base, a buried collector in the thin semiconductor layer to contact the insulating layer, a collector contacting the buried collector, and emitter, collector and base contacts. The active transistor area is configured to operate at an emitter current at least in the order of mA (milli-ampere). An isolation trench extends through the semiconductor layer to the insulating layer and surrounds the active transistor area with a distance in the order of ?m (micron) from the active transistor area and with a space area of more than 50 ?m2 between the active transistor area and the isolation trench.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: September 13, 2011
    Assignees: Hitachi ULSI Systems Co., Ltd., Hitachi, Ltd.
    Inventors: Mitsuru Arai, Shinichiro Wada, Hideaki Nonami
  • Publication number: 20100314712
    Abstract: A semiconductor device includes a lower substrate, a thin semiconductor layer and an insulating layer formed between the lower substrate and the semiconductor layer. An active transistor area is formed with a base formed along a surface of the semiconductor layer, an emitter region formed in the base, a buried collector in the thin semiconductor layer to contact the insulating layer, a collector contacting the buried collector, and emitter, collector and base contacts. The active transistor area is configured to operate at an emitter current at least in the order of mA (milli-ampere). An isolation trench extends through the semiconductor layer to the insulating layer and surrounds the active transistor area with a distance in the order of ?m (micron) from the active transistor area and with a space area of more than 50 ?m2 between the active transistor area and the isolation trench.
    Type: Application
    Filed: April 13, 2010
    Publication date: December 16, 2010
    Inventors: Mitsuru Arai, Shinichiro Wada, Hideaki Nonami
  • Patent number: 7696582
    Abstract: A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors connected in parallel is removed and the plurality of unit bipolar transistors connected in series are entirely surrounded with one device isolation trench.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: April 13, 2010
    Assignees: Hitachi ULSI Systems Co., Ltd., Hitachi, Ltd.
    Inventors: Mitsuru Arai, Shinichiro Wada, Hideaki Nonami
  • Patent number: 7576406
    Abstract: A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: August 18, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Hideaki Nonami, Masato Hamamoto
  • Patent number: 7569895
    Abstract: A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors connected in parallel is removed and the plurality of unit bipolar transistors connected in series are entirely surrounded with one device isolation trench.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: August 4, 2009
    Assignees: Hitachi ULSI Systems Co., Ltd., Hitachi, Ltd.
    Inventors: Mitsuri Arai, Shinichiro Wada, Hideaki Nonami
  • Publication number: 20090160016
    Abstract: A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors connected in parallel is removed and the plurality of unit bipolar transistors connected in series are entirely surrounded with one device isolation trench.
    Type: Application
    Filed: February 18, 2009
    Publication date: June 25, 2009
    Inventors: Mitsuru ARAI, Shinichiro Wada, Hideaki Nonami
  • Publication number: 20080036032
    Abstract: A trimming element for trimming a redundant circuit and a high-accuracy resistance in consideration of the stability and the ease of fuse cutting, and more specifically a trimming element which is easily formed by an existing process. An SOI substrate, a heater connected to the SOI substrate, and a fuse connected to the heater are formed.
    Type: Application
    Filed: June 26, 2007
    Publication date: February 14, 2008
    Inventor: Hideaki Nonami
  • Publication number: 20060175635
    Abstract: A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors connected in parallel is removed and the plurality of unit bipolar transistors connected in series are entirely surrounded with one device isolation trench.
    Type: Application
    Filed: January 19, 2006
    Publication date: August 10, 2006
    Inventors: Mitsuru Arai, Shinichiro Wada, Hideaki Nonami
  • Publication number: 20040183159
    Abstract: A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.
    Type: Application
    Filed: February 9, 2004
    Publication date: September 23, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Hideaki Nonami, Masato Hamamoto