Patents by Inventor Hideaki Ohmura

Hideaki Ohmura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7321955
    Abstract: The storage control device of the present invention controls a plurality of storage devices. The storage control device comprises an LRU write-back unit writing back data stored in the cache memory of the storage control device into the plurality of storage devices by the LRU method, and a write-back schedule processing unit selecting a storage device with a small number of write-backs executed by the LRU write-back unit and writing back data into the selected storage device.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: January 22, 2008
    Assignee: Fujitsu Limited
    Inventor: Hideaki Ohmura
  • Publication number: 20060212669
    Abstract: The present invention provides a control method for a storage system comprising the first process for copying information stored by a first storage apparatus which is accessed by an upper echelon apparatus to a second storage apparatus, the second process for judging whether or not storage contents of the first and second storage apparatuses are identical when a fault occurs in the first storage apparatus, and the third process for controlling so that the upper echelon apparatus accesses the second storage apparatus in place of the first storage apparatus if the storage contents of the first and second storage apparatuses are identical.
    Type: Application
    Filed: September 30, 2005
    Publication date: September 21, 2006
    Applicant: Fujitsu Limited
    Inventors: Koji Uchida, Hideaki Ohmura, Yoshinari Shinozaki, Mihoko Wada
  • Publication number: 20050223168
    Abstract: The storage control device of the present invention controls a plurality of storage devices. The storage control device comprises an LRU write-back unit writing back data stored in the cache memory of the storage control device into the plurality of storage devices by the LRU method, and a write-back schedule processing unit selecting a storage device with a small number of write-backs executed by the LRU write-back unit and writing back data into the selected storage device.
    Type: Application
    Filed: September 8, 2004
    Publication date: October 6, 2005
    Applicant: FUJITSU LIMITED
    Inventor: Hideaki Ohmura
  • Patent number: 6237046
    Abstract: When an input/output request of a channel adapter causes a mishit on a cache and a staging amount by a device adapter reaches a predetermined amount, the cache is set into a hit status and the channel adapter is reactivated. By receiving a hit response, the reactivated channel adapter executes an input and an output for the cache and the staging of the channel adapter in parallel. A defective/alternating track management table which corresponds to track data stored in a cache memory and has each of addresses of a defective track and an alternating track and flag information showing a link state between both of the defective track and the alternating track is provided for an input/output controller. For a retrieving request in which the defective track address is designated, the defective/alternating track management table is retrieved and the corresponding alternating track address is obtained, thereby judging the presence or absence of a registration of a hash table.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: May 22, 2001
    Assignee: Fujitsu Limited
    Inventors: Hideaki Ohmura, Kazuma Takatsu, Wasako Fueda
  • Patent number: 5761531
    Abstract: When an input/output request of a channel adapter causes a mishit on a cache and a staging amount by a device adapter reaches a predetermined amount, the cache is set into a hit status and the channel adapter is reactivated. By receiving a hit response, the reactivated channel adapter executes an input and an output for the cache and the staging of the channel adapter in parallel. A defective/alternating track management table which corresponds to track data stored in a cache memory and has each of addresses of a defective track and an alternating track and flag information showing a link state between both of the defective track and the alternating track is provided for an input/output controller. For a retrieving request in which the defective track address is designated, the defective/alternating track management table is retrieved and the corresponding alternating track address is obtained, thereby judging the presence or absence of a registration of a hash table.
    Type: Grant
    Filed: June 7, 1996
    Date of Patent: June 2, 1998
    Assignee: Fujitsu Limited
    Inventors: Hideaki Ohmura, Kazuma Takatsu, Wasako Fueda
  • Patent number: 5724542
    Abstract: An ID portion indicating the corresponding relationship between the number of a record contained in an FBA block and the position of the record is provided at the beginning of the FBA block. When a seek command has been issued by a host apparatus in the CKD format, a device adapter obtains the FBA block number corresponding to the parameter value (CCHH) of a head positioning command and positions a head at the FBA block of this number. Next, the device adapter obtains the FBA block number corresponding to the parameter value (sector value) of a set-sector command, reads one CKD track of blocks from the FBA block designated by the FBA block number and develops these blocks in a cache memory. A channel adapter searches the cache memory for a commanded record by referring to the information in the ID portion.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: March 3, 1998
    Assignee: Fujitsu Limited
    Inventors: Yuichi Taroda, Kazuma Takatsu, Sanae Kamakura, Nobukazu Kirigaya, Hideaki Ohmura