Abstract: A vehicle control device includes a processor and memory. The memory stores relation-defining data for defining a relation between a state of a vehicle and an action variable that is a variable relating to operations of a transmission installed in the vehicle. The processor is configured to execute acquisition processing, operation processing, reward calculation processing, updating processing, counting processing, and limiting processing. The processor is configured to output the relation-defining data updated so that an expected income is increased when the transmission is operated following the relation-defining data, based on an updating map.

Abstract: A signal generation system maintains a phase relationship between output signals of first and second signal generators even when the sampling clock frequency is changed. The signal generators are coupled via a communication means including a dedicated cable where the delay amount of the communication means is known and fixed. The first signal generator provides sampling clock, sequence clock and trigger/event signals to the second signal generator and CPUs of the generators share information via the cable. When the frequency of the sampling clock is changed, the CPU of the first or second signal generator calculates the clock number of the frequency changed sampling clock equivalent to the delay amount of the communication means. A delay circuit of the first signal generator 100 delays the waveform data by one sampling clock based on the calculated value for adjusting phase relationship between the waveform data in the signal generators 1.

Abstract: A signal generation system maintains a phase relationship between output signals of first and second signal generators even when the sampling clock frequency is changed. The signal generators are coupled via a communication means including a dedicated cable where the delay amount of the communication means is known and fixed. The first signal generator provides sampling clock, sequence clock and trigger/event signals to the second signal generator and CPUs of the generators share information via the cable. When the frequency of the sampling clock is changed, the CPU of the first or second signal generator calculates the clock number of the frequency changed sampling clock equivalent to the delay amount of the communication means. A delay circuit of the first signal generator 100 delays the waveform data by one sampling clock based on the calculated value for adjusting phase relationship between the waveform data in the signal generators 1.

Abstract: A jitter inducing circuit receives a reference pulse train and induces desired amounts of jitter to the rising and/or falling edges of the pulses. First and second delay blocks 16 and 18 alternately delay the selected edge or edges of the provided reference pulse train interval by preset delay times for every interval. A signal composer 46 composes the outputs of the first and second delay blocks 16 and 18. A delay time setup circuit controls the delay times of the delay blocks 16 and 18. The delay times may change for each interval as a function of time so as to trace a desired function such as a sinusoidal or triangular function.

Abstract: A jitter inducing circuit receives a reference pulse train and induces desired amounts of jitter to the rising and/or falling edges of the pulses. First and second delay blocks 16 and 18 alternately delay the selected edge or edges of the provided reference pulse train interval by preset delay times for every interval. A signal composer 46 composes the outputs of the first and second delay blocks 16 and 18. A delay time setup circuit controls the delay times of the delay blocks 16 and 18. The delay times may change for each interval as a function of time so as to trace a desired function such as a sinusoidal or triangular function.

Abstract: A thermoelectric module of a Peltier element is placed on a rectangular-projected portion of a highly thermally conductive module base made from aluminum. A heat-absorbing fin member used as a cold-side absorber is fixed to the rectangular-projected portion of the module base while a radiating fin member used as a hot-side radiator is fixed to a flat portion of the module base.