Patents by Inventor Hideaki Sadamatsu

Hideaki Sadamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5764073
    Abstract: A method for estimating the reliability of modular circuits by conducting an accelerated life test of components comprising a modular circuit, applying the acceleration factor, etc. on test data thus obtained, and calculating a time to reach a predetermined rate of deterioration as the life time. By adding actual working conditions to the rate of deterioration, a minimum value for determining the deterioration of characteristics is obtained. A component having a value not higher than the minimum value or a rate not lower than the characteristic rate of degradation is then mounted on a printed circuit board comprising the modular circuit, to confirm whether the modular circuit functions normally.
    Type: Grant
    Filed: May 22, 1996
    Date of Patent: June 9, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hideaki Sadamatsu
  • Patent number: 5391944
    Abstract: In a tone control circuit of luminance signals, an adjusting current is used to add to or subtract from input signals with a gain control. Output signals are thus controlled to have a predetermined gradient based on an arbitrary output setting voltage against the input signals, and an input-output characteristic represented by an arbitrary line graph is obtained by plural gradient adjusting circuits.
    Type: Grant
    Filed: December 10, 1992
    Date of Patent: February 21, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hideaki Sadamatsu
  • Patent number: 5307166
    Abstract: In a tone control circuit of luminance signals, input-output characteristic having an arbitrary line graph is obtained by plural gradient adjusting circuits in response to frequencies of brightness of the luminance signals which are detected by plural IRE circuits.
    Type: Grant
    Filed: November 10, 1992
    Date of Patent: April 26, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hideaki Sadamatsu
  • Patent number: 5299008
    Abstract: A tone correction circuit for a luminance signal which can provide several shapes of correction characteristics. The tone correction circuit comprises a circuit in which the current increases at a first specified voltage or higher and decreases at a second specified voltage or higher so that the current is outputted in a specified range and also provided is a circuit which serves to increase the current at the second specified voltage or higher. Thus, without changing the output voltage at the midpoint, the correction amounts at the minimum point and midpoint, the shifting amount of the midpoint, the correction amounts from to the maximum point and the correction amount at the maximum point, can be controlled so that an optimum output waveform can be obtained in accordance with a scene, and particularly, fuzzy control for the scene can be efficiently made.
    Type: Grant
    Filed: February 14, 1992
    Date of Patent: March 29, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hideaki Sadamatsu
  • Patent number: 5262862
    Abstract: A black compensation circuit for compensating a luminance signal which is subjected to edge enhancement, comprises: a black-level expanding circuit responsive to a control signal including an edge enhancement component and the luminance signal for performing expansion of a tone of a black portion of the luminance signal and for performing conversion of the luminance signal into a black-level expanded signal in the absence of the control signal; a low-pass filter circuit for low-pass filtering the luminance signal to remove the edge enhancement component; a detection circuit responsive to an output of the low-pass filter circuit for detecting the blackest level for a given interval; and a comparing circuit for comparing the blackest level with a given level to produce the control signal, the black-level expanding circuit stopping the expansion and the conversion in the presence of the control signal.
    Type: Grant
    Filed: July 18, 1991
    Date of Patent: November 16, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Sadamatsu, Atsuhisa Kageyama
  • Patent number: 5237195
    Abstract: A semiconductor integrated circuit arrangement prevents the occurrence of latch up. The circuit includes a first semiconductor island of a first conductivity type and a second semiconductor island of the first conductivity type located within a base semiconductor region of a second conductivity type. A resistive diffusion region of the second conductivity type is located within the first semiconductor island region. The second semiconductor region is connected to ground. A high potential electrode connected to the resistive diffusion region is also connected to the first semiconductor island region. In this manner, an emitter and a base of a parasitic transistor of the integrated circuit are connected together to prevent the parasitic transistor from operating in a conductive state, thereby preventing latch up.
    Type: Grant
    Filed: July 15, 1991
    Date of Patent: August 17, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hideaki Sadamatsu
  • Patent number: 5223927
    Abstract: The average picture level (APL) of a video luminance signal is detected, wherein the output of a first current mirror circuit used as the load of a differential amplifying circuit is fed into a smoothing circuit via a second current mirror circuit. The direct current voltage of the output and the detection voltage amplitude may be optionally set without causing an offset voltage in the output average picture level voltage, with the current flowing through the second current mirror circuit being made zero at the time of APL=0%.
    Type: Grant
    Filed: July 10, 1991
    Date of Patent: June 29, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsuhisa Kageyama, Hideaki Sadamatsu
  • Patent number: 4536950
    Abstract: In making a vertical bipolar transistors, after forming by diffusion process a region to become inactive base region an oxide film is selectively formed on the region, thereafter an ion implantation is carried out to produce regions which become the active base region and emitter region by using the oxide film; thereby such a configuration is formed so that defect part (108) induced at the time of the ion implantation is confined in the emitter region, thereby minimizing the leakage current at the PN junction, and hence assuring production of high performance and high reliability semiconductor devices; further, a high integration is attained by adopting self-alignment in forming emitter contact.
    Type: Grant
    Filed: February 8, 1984
    Date of Patent: August 27, 1985
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Sadamatsu, Michihiro Inoue, Akihiro Kanda, Akira Matsuzawa