Abstract: A data transfer method is disclosed in a multi-chip semiconductor device which comprises a plurality of inter-chip wires. First, a test is conducted to determine whether or not each inter-chip wire is capable of normally transferring data, on circuits arranged on chips between which the inter-chip wire is connected. When an inter-chip wire incapable of normally transferring data exists, the data transfer speed of the buffer circuit that is on the chip on the transmission and that is connected to an inter-chip wire capable of normally transferring data is increased. The buffer circuit, whose data transfer speed has been increased, transfers data which would otherwise be transferred through the inter-chip wire incapable of normally transferring data, together with the data which should be transferred thereby, to the chip on the reception side chip through an inter-chip wire connected to the buffer circuit at the data transfer speed.

Abstract: A semiconductor device is provided with a first wiring (110) between chips, for electrically connecting a first semiconductor chip with a second semiconductor chip; an auxiliary second wiring (120) between chips; a test signal generating circuit (4) for transmitting a test signal from the first semiconductor chip to the second semiconductor chip through the first wiring; a judging circuit (8), which outputs a first control signal in the case of receiving the test signal through the first wiring, and outputs a second control signal, i.e.

Abstract: A semiconductor device, which allows a bank interleaving operation by issuing a write command and a read command to different banks while switching them without a waiting time to thereby prevent a drop in data transfer efficiency, is provided. The semiconductor device includes: a memory chip with banks each including at least one memory cell; a logic chip; and data buses, provided corresponding to the banks, for transmitting/receiving write data and read data between the banks and the logic chip. The logic chip includes: a writing data bus for transmitting write data to the memory chip via a data bus; a reading data bus for receiving read data from the memory chip via a data bus; and a switch for, corresponding to a write command or a read command to a bank, connecting the writing data bus or the reading data bus to a data bus connected to the bank.

Abstract: A network monitoring system which monitors activities on a network with optimal coverage and frequency, depending on the current state of the network. A monitoring policy setting unit sets a specific monitoring policy that includes: which object to watch, which item of that object to monitor, and how frequent it should be. According to this policy, a monitoring unit carries out monitoring of the network. The monitoring result is passed to a monitoring policy changing unit, which changes the current monitoring policy being set in the monitoring policy setting unit. Some related resources on the network may also be reconfigured according to the reported monitoring result, by a resource setup changing unit. An event detector detects a particular event occurred in the network resources and notifies the monitoring policy changing unit of the occurrence, so that the monitoring policy will be changed accordingly.

Abstract: A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.

Abstract: In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.

Abstract: An airbag, which is folded and assembled elongatedly, is deployed along a side window. The airbag has a folded portion and a pleated portion which wraps the folded portion under the assembled condition. The airbag also has an inner tube which is provided from the inside of an infusion portion to the inside of an upstream portion of an inflating portion. The inner tube prevents that the airbag is damaged by heat of inflation gas. When the airbag is assembled, the inner tube is positioned along a first fabric, which is developed so that the surface of the first fabric faces an inside of a vehicle compartment, by the infused fluid. Deployment performance of the airbag (curtain airbag deploying along a side window of an automobile) is improved.

Abstract: A p-type semiconductor barrier layer is provided in the vicinity of undoped quantum dots, and holes in the p-type semiconductor barrier layer are injected in advance in the ground level of the valence band of the quantum dots. Lowering the threshold electron density of conduction electrons in the ground level of the conduction band of quantum dots in this way accelerates the relaxation process of electrons from an excited level to the ground level in the conduction band.

Abstract: The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.

Abstract: A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

Abstract: A p-type semiconductor barrier layer is provided in the vicinity of undoped quantum dots, and holes in the p-type semiconductor barrier layer are injected in advance in the ground level of the valence band of the quantum dots. Lowering the threshold electron density of conduction electrons in the ground level of the conduction band of quantum dots in this way accelerates the relaxation process of electrons from an excited level to the ground level in the conduction band.

Abstract: A pivoting arrangement for connecting an actuator to the outboard drive portion of a marine propulsion unit and more particularly to an arrangement for strengthening the pivotal connection without significantly increasing its size and by simplifying its construction to reduce cost.

Abstract: A pivoting arrangement for connecting an actuator to the outboard drive portion of a marine propulsion unit and more particularly to an arrangement for strengthening the pivotal connection without significantly increasing its size and by simplifying its construction to reduce cost.

Abstract: A tilt and trim system for the outboard drive of a marine propulsion unit wherein the popping up action is effectively damped without positive stops that could cause abrupt stopping and possible damage.

Abstract: An object of the present invention is to provide a novel DNA sequence having a flower organ-specific promoter activity which makes it possible to express a foreign gene specifically in pistil or lodicule, this enabling genetic manipulation. The present invention provides a DNA fragment comprising the sequence of positions 1 to 5369 in the nucleotide sequence represented by SEQ ID NO:3 in Sequence Listing, the sequence of positions 3335 to 5108 therein, a part of these sequences or a sequence derived from these sequences by deletion, substitution, insertion or addition of one or more nucleotides and having a promoter activity; and a flower organ-specific promoter sequence which can be identified from among sequences obtained by screening a genomic library of rice or other plants by using as a probe the nucleotide sequence as described above or a part thereof.

Abstract: An improved hydraulic system for a marine propulsion unit where it is insured that leakage of the shuttle valve will not permit the propulsion unit to move from the desired position by having a series of shuttle piston operated check valves inn series flow between the pump and the hydraulic unit that controls the position.

Abstract: A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film.

Abstract: A very effective unit for adjusting the condition of a marine propulsion device that is constructed in such a way to protect the various components from wear caused by foreign particles that may be formed during its life by trapping the particles in a cavity formed in an upper surface of an actuating piston.

Abstract: A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.

Abstract: A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.