Patents by Inventor Hideaki Sunohara

Hideaki Sunohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10885820
    Abstract: Provided is a method of inspecting pixels. The method includes the step of applying a switching signal to gate electrodes of inspection transistors and the step of applying an inspection data signal to one or more of source electrodes of the inspection transistors. A voltage applied to the gate electrodes is controlled under the switching signal and the inspection data signal.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: January 5, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Hideaki Sunohara
  • Patent number: 10748498
    Abstract: A lower input electrode is electrically connected to a lower end portion of a common electrode. An upper input electrode and an output electrode are electrically connected to an upper end portion of the common electrode. The lower input electrode, the upper input electrode, and the output electrode are electrically connected to one another through only the common electrode.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 18, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Hideaki Sunohara
  • Publication number: 20190147817
    Abstract: A lower input electrode is electrically connected to a lower end portion of a common electrode. An upper input electrode and an output electrode are electrically connected to an upper end portion of the common electrode. The lower input electrode, the upper input electrode, and the output electrode are electrically connected to one another through only the common electrode.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 16, 2019
    Inventor: HIDEAKI SUNOHARA
  • Publication number: 20190147780
    Abstract: Provided is a method of inspecting pixels. The method includes the step of applying a switching signal to gate electrodes of inspection transistors and the step of applying an inspection data signal to one or more of source electrodes of the inspection transistors. A voltage applied to the gate electrodes is controlled under the switching signal and the inspection data signal.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 16, 2019
    Inventor: HIDEAKI SUNOHARA
  • Patent number: 8293590
    Abstract: An active matrix substrate 40 according to the present invention includes a conductive film 44 and a wiring 80 for supplying a signal to the conductive film 44, characterized in that the wiring 80 includes a first conductive layer 61 and a second conductive layer 62 having a relatively large line width in comparison with the first conductive layer 61 and laminated so as to cover the first conductive layer 61, and the conductive film 44 is arranged in a matrix pattern, and at least a portion of the conductive film 44 is disposed overlapping the wiring 80.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: October 23, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hideaki Sunohara
  • Publication number: 20110147751
    Abstract: A display panel substrate in which the width of a trace can be reduced without impairing a signal transfer capability of the trace. A display panel substrate (1) includes abase (12) that has a substantially semicircular cross-section in a direction perpendicular to a longitudinal direction of the base (12), and a trace (13) that has a thin film shape and has a longitudinal direction substantially parallel to the longitudinal direction of the base (12), at least a portion of the trace being superimposed on the base 12, at least a portion of the trace having a substantially arc cross-section in a direction perpendicular to the longitudinal direction of the base (12).
    Type: Application
    Filed: April 22, 2009
    Publication date: June 23, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Hideaki Sunohara
  • Publication number: 20110080570
    Abstract: An exposure apparatus and an exposure method by which alignment of regions of a substrate that are to be exposed by optical systems can be performed with accuracy even if the substrate is deformed nonuniformly within a plane. A step-and-scan exposure apparatus (1) for performing exposure on a substrate (5) that is a subject to be exposed includes a plurality of mark detection systems (20) capable of detecting alignment marks (52) provided on the substrate (5), and a plurality of projection optical systems (15) capable of illuminating corresponding projection regions (F1 to F7) set on the subject (5) with light energy, wherein the mark detection systems (20) are disposed between the adjacent projection optical systems (15) and on right and left sides of the endmost projection optical systems (15).
    Type: Application
    Filed: April 22, 2009
    Publication date: April 7, 2011
    Inventor: Hideaki Sunohara
  • Publication number: 20110070399
    Abstract: A substrate for a display panel that is capable of increasing an auxiliary capacitance of a capacitor without increasing an outside dimension of the capacitor. The substrate includes a first conductive film (141), a second conductive film (142) that is superimposed on the first conductive film (141) and includes an opening, and second and third insulating films (18) (19) that are superimposed on the first and second conductive films (141) (142) and each include openings (contact holes), the first conductive film (141) being exposed from the openings of the second conductive film (142) and the second and third insulating films (18) (19), a rim of the opening of the second conductive film (142) being covered with a protruding portion (191) of the third insulating film (19).
    Type: Application
    Filed: April 22, 2009
    Publication date: March 24, 2011
    Inventor: Hideaki Sunohara
  • Publication number: 20100207130
    Abstract: An active matrix substrate 40 according to the present invention includes a conductive film 44 and a wiring 80 for supplying a signal to the conductive film 44, characterized in that the wiring 80 includes a first conductive layer 61 and a second conductive layer 62 having a relatively large line width in comparison with the first conductive layer 61 and laminated so as to cover the first conductive layer 61, and the conductive film 44 is arranged in a matrix pattern, and at least a portion of the conductive film 44 is disposed overlapping the wiring 80.
    Type: Application
    Filed: May 23, 2008
    Publication date: August 19, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Hideaki Sunohara