Patents by Inventor Hideaki Tamimoto

Hideaki Tamimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378032
    Abstract: To manufacture a semiconductor device, a first heat treatment for curing a first adhesive material of a conductive paste type is performed, after a semiconductor chip is mounted on a die pad of a lead frame via the first adhesive material. After that, a metal plate is disposed on a pad of the semiconductor chip such that the metal plate faces the pad of the semiconductor chip via a second adhesive material of a conductive paste type, and a second heat treatment is performed for curing each of the first adhesive material and the second adhesive material. A time of the first heat treatment is less than a time of the second heat treatment. After the first adhesive material is cured by the first heat treatment, the first adhesive material is further cured by the second heat treatment.
    Type: Application
    Filed: February 28, 2023
    Publication date: November 23, 2023
    Inventors: Kosuke KITAICHI, Masatoshi SUGIURA, Hideaki TAMIMOTO, Takehiko MAEDA, Keita TAKADA, Yoshitaka KYOUGOKU
  • Patent number: 9899301
    Abstract: A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: February 20, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsuhito Kamachi, Hideaki Tamimoto
  • Publication number: 20180019189
    Abstract: A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.
    Type: Application
    Filed: September 21, 2017
    Publication date: January 18, 2018
    Inventors: Katsuhito KAMACHI, Hideaki TAMIMOTO
  • Patent number: 9806007
    Abstract: A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.
    Type: Grant
    Filed: December 4, 2016
    Date of Patent: October 31, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhito Kamachi, Hideaki Tamimoto
  • Publication number: 20170221803
    Abstract: A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.
    Type: Application
    Filed: December 4, 2016
    Publication date: August 3, 2017
    Inventors: Katsuhito KAMACHI, Hideaki TAMIMOTO
  • Publication number: 20110073921
    Abstract: The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second branch. In order to do bonding of the Al ribbon to the source pad of the silicon chip, and the source post of the lead frame, first, the first branch and second branch of the wedge tool are contacted by pressure to Al ribbon on the source pad, and supersonic vibration is applied to it. Subsequently, the first branch is contacted by pressure to Al ribbon on the source post, and supersonic vibration is applied to it. Here, since the width of the first branch is narrower than the width of the source post, Al ribbon is not joined at the end surface of the width direction of the source post.
    Type: Application
    Filed: December 7, 2010
    Publication date: March 31, 2011
    Inventors: Hideaki TAMIMOTO, Takumi SOBA, Toru UEGURI, Kazuo KUDO
  • Patent number: 7863107
    Abstract: The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second branch. In order to do bonding of the Al ribbon to the source pad of the silicon chip, and the source post of the lead frame, first, the first branch and second branch of the wedge tool are contacted by pressure to Al ribbon on the source pad, and supersonic vibration is applied to it. Subsequently, the first branch is contacted by pressure to Al ribbon on the source post, and supersonic vibration is applied to it. Here, since the width of the first branch is narrower than the width of the source post, Al ribbon is not joined at the end surface of the width direction of the source post.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Tamimoto, Takumi Soba, Toru Ueguri, Kazuo Kudo
  • Publication number: 20090152697
    Abstract: The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second branch. In order to do bonding of the Al ribbon to the source pad of the silicon chip, and the source post of the lead frame, first, the first branch and second branch of the wedge tool are contacted by pressure to Al ribbon on the source pad, and supersonic vibration is applied to it. Subsequently, the first branch is contacted by pressure to Al ribbon on the source post, and supersonic vibration is applied to it. Here, since the width of the first branch is narrower than the width of the source post, Al ribbon is not joined at the end surface of the width direction of the source post.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 18, 2009
    Inventors: Hideaki Tamimoto, Takumi Soba, Toru Ueguri, Kazuo Kudo