Patents by Inventor Hideaki Tomikawa

Hideaki Tomikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8576219
    Abstract: An image processing apparatus able to continuously generate region data, able to eliminate wasteful processing due to invalid regions, and able to efficiently draw an image, is provided with a triangle digital differential analyzer (DDA) circuit for generating region data increased by at least one unit square region worth of data based on set-up data including a change data input from a DDA set-up circuit in a case where at least one pixel is located inside a triangle in a unit square region including a plurality of pixels, storing the region data, further dividing the stored region data into usual region data equivalent to the unit square regions, and outputting the same as DDA data to a texture engine circuit, and a method of the same.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: November 5, 2013
    Assignee: Sony Corporation
    Inventors: Tetsugo Inada, Hideaki Tomikawa, Junichi Fujita
  • Patent number: 7791604
    Abstract: A graphics drawing apparatus able to reduce the amount of data transferred, able to realize a lower power consumption, and consequently able to achieve an improvement of performance of the system as a whole, provided with address generator for automatically generating addresses of drawing parameter registers required for the drawing in a defined sequence of drawing parameters according to address data and a specified drawing type; a register address selector for selecting either of the address data for specifying the register addresses of the address generator transferred through a general purpose bus or the address data for specifying the register address of the address generator by a former engine and inputting the same to the address generator; and a drawing data selector for selecting either of the drawing parameter data transferred through the general purpose bus or the drawing parameter data from the former engine and inputting the same to the drawing engine, and a method of the same.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 7, 2010
    Assignee: Sony Corporation
    Inventors: Hideaki Tomikawa, Junichi Fujita
  • Patent number: 7151862
    Abstract: Texture data filtered according to each of different reduction ratio are stored in a texture buffer. A texture mapping apparatus (an lod calculating apparatus) calculates an lod (Level Of Detail) which represents a reduction ratio of each pixel of a polygon. The calculation does not include a divisional calculation. In other words, the lod calculating apparatus does not need many multipliers, as compared with a case in which an operation including a divisional calculation, thereby enabling the down-sizing of the lod calculating apparatus.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: December 19, 2006
    Assignee: Sony Corporation
    Inventors: Tanio Nagasaki, Hideaki Tomikawa, Seigo Iwasaki, Tetsuo Motomura, Masahiro Igarashi
  • Publication number: 20050237333
    Abstract: A graphics drawing apparatus able to reduce the amount of data transferred, able to realize a lower power consumption, and consequently able to achieve an improvement of performance of the system as a whole, provided with address generator for automatically generating addresses of drawing parameter registers required for the drawing in a defined sequence of drawing parameters according to address data and a specified drawing type; a register address selector for selecting either of the address data for specifying the register addresses of the address generator transferred through a general purpose bus or the address data for specifying the register address of the address generator by an former engine and inputting the same to the address generator; and a drawing data selector for selecting either of the drawing parameter data transferred through the general purpose bus or the drawing parameter data from the former engine and inputting the same to the drawing engine, and a method of the same.
    Type: Application
    Filed: June 30, 2005
    Publication date: October 27, 2005
    Inventors: Hideaki Tomikawa, Junichi Fujita
  • Patent number: 6950102
    Abstract: A graphics drawing apparatus able to reduce the amount of data transferred, able to realize a lower power consumption, and consequently able to achieve an improvement of performance of the system as a whole, provided with address generator for automatically generating addresses of drawing parameter registers required for the drawing in a defined sequence of drawing parameters according to address data and a specified drawing type; a register address selector for selecting either of the address data for specifying the register addresses of the address generator transferred through a general purpose bus or the address data for specifying the register address of the address generator by a former engine and inputting the same to the address generator; and a drawing data selector for selecting either of the drawing parameter data transferred through the general purpose bus or the drawing parameter data from the former engine and inputting the same to the drawing engine, and a method of the same.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: September 27, 2005
    Assignee: Sony Corporation
    Inventors: Hideaki Tomikawa, Junichi Fujita
  • Publication number: 20040004620
    Abstract: An image processing apparatus able to continuously generate region data, able to eliminate wasteful processing due to invalid regions, and able to efficiently draw an image, provided with a triangle DDA circuit for generating large region data increased by at least one unit square regions worth of data based on set-up data including a change data input from a DDA set-up circuit in a case where at least one pixel is located inside a triangle in a unit square region including a plurality of pixels, storing the large region data, further dividing the stored large region data into usual region data equivalent to the unit square regions, and outputting the same as DDA data to a texture engine circuit, and a method of the same.
    Type: Application
    Filed: February 5, 2003
    Publication date: January 8, 2004
    Inventors: Tetsugo Inada, Hideaki Tomikawa, Junichi Fujita
  • Publication number: 20030169266
    Abstract: A graphics drawing apparatus able to reduce the amount of data transferred, able to realize a lower power consumption, and consequently able to achieve an improvement of performance of the system as a whole, provided with address generator for automatically generating addresses of drawing parameter registers required for the drawing in a defined sequence of drawing parameters according to address data and a specified drawing type; a register address selector for selecting either of the address data for specifying the register addresses of the address generator transferred through a general purpose bus or the address data for specifying the register address of the address generator by an former engine and inputting the same to the address generator; and a drawing data selector for selecting either of the drawing parameter data transferred through the general purpose bus or the drawing parameter data from the former engine and inputting the same to the drawing engine, and a method of the same.
    Type: Application
    Filed: December 27, 2002
    Publication date: September 11, 2003
    Inventors: Hideaki Tomikawa, Junichi Fujita
  • Publication number: 20030117399
    Abstract: Texture data filtered according to each of different reduction ratio are stored in a texture buffer. A texture mapping apparatus (an lod calculating apparatus) calculates an lod (Level Of Detail) which represents a reduction ratio of each pixel of a polygon. The calculation does not include a divisional calculation. In other words, the lod calculating apparatus does not need many multipliers, as compared with a case in which an operation including a divisional calculation, thereby enabling the down-sizing of the lod calculating apparatus.
    Type: Application
    Filed: November 19, 2002
    Publication date: June 26, 2003
    Inventors: Tanio Nagasaki, Hideaki Tomikawa, Seigo Iwasaki, Tetsuo Motomura, Masahiro Igarashi
  • Patent number: 6409642
    Abstract: An assembling device for supplying and assembling a part on an object has a table and a first moving portion disposed above the table, where the first moving portion includes a guide and a movable body. The guide extends in a first direction parallel to a surface of the table out of a range in which the table is positioned. The movable body is movable to a position out of the range in which the table is positioned. The assembling device also has a second moving portion disposed on the table and movable in a second direction transverse to the first direction, the object being mounted on the second moving portion.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: June 25, 2002
    Assignee: Sony Corporation
    Inventors: Morio Tominaga, Katsuya Arai, Shoichi Hayashi, Kenichi Kato, Tsuyoshi Inoue, Hiroyuki Suzuki, Tetsuo Higewake, Hideaki Tomikawa, Takeshi Tokita, Norifumi Otsuka, Hiroshi Teranishi
  • Publication number: 20010002380
    Abstract: An assembling device for supplying and assembling a part on an object has a table and a first moving means disposed above the table, wherein the first moving means includes a guide and a movable body. The guide extends in a first direction parallel to a surface of the table out of a range in which the table is positioned. The movable body is movable to a position out of the range in which the table is positioned. The assembling device also has a second moving means disposed on the table and movable in a second direction transverse to the first direction, the object being mounted on the second moving means.
    Type: Application
    Filed: May 18, 1999
    Publication date: May 31, 2001
    Applicant: kananen
    Inventors: MORIO TOMINAGA, KATSUYA ARAI, SHOICHI HAYASHI, KENICHI KATO, TSUYOSHI INOUE, HIROYUKI SUZUKI, TETSUO HIGEWAKE, HIDEAKI TOMIKAWA, TAKESHI TOKITA, NORIFUMI OTSUKA, HIROSHI TERANISHI
  • Patent number: D418528
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: January 4, 2000
    Assignee: Sony Corporation
    Inventors: Hiroshi Honjo, Morio Tominaga, Kenichi Kato, Tsuyoshi Inoue, Hiroshi Teranishi, Takashi Tokita, Hideaki Tomikawa, Hiroyuki Suzuki, Katsuya Arai, Norifumi Otsuka, Shoichi Hayashi, Tetsuo Higewake