Patents by Inventor Hideaki Uemura
Hideaki Uemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7800960Abstract: A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage.Type: GrantFiled: February 26, 2008Date of Patent: September 21, 2010Assignee: NEC Electronics CorporationInventors: Yasuhiro Tonda, Hidetoshi Ozoe, Hideaki Uemura, Junichi Yamada, Kenji Hibino, Tatsuya Saito
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Publication number: 20080205167Abstract: A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage.Type: ApplicationFiled: February 26, 2008Publication date: August 28, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Yasuhiro Tonda, Hidetoshi Ozoe, Hideaki Uemura, Junichi Yamada, Kenji Hibino, Tatsuya Saito
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Patent number: 6809634Abstract: A pulse signal, having a buzzer-driving frequency, for driving a buzzer (3) is generated by a free running timer of a timer management section of a microcomputer (1). The timer management section operates independently of software processing of the microcomputer (1). A transistor (2) is turned on and off by the pulse signal having the buzzer-driving frequency. Accordingly, electricity flows through the buzzer (3). The buzzer (3) in turn, generates a sound.Type: GrantFiled: April 24, 2002Date of Patent: October 26, 2004Assignee: Sumitomo Wiring Systems, LtdInventors: Hideaki Uemura, Kenji Wakana
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Publication number: 20020180593Abstract: A pulse signal, having a buzzer-driving frequency, for driving a buzzer (3) is generated by a free running timer of a timer management section of a microcomputer (1). The timer management section operates independently of software processing of the microcomputer (1). A transistor (2) is turned on and off by the pulse signal having the buzzer-driving frequency. Accordingly, electricity flows through the buzzer (3). The buzzer (3) in turn, generates a sound.Type: ApplicationFiled: April 24, 2002Publication date: December 5, 2002Inventors: Hideaki Uemura, Kenji Wakana
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Patent number: 6242957Abstract: According to one embodiment, a master-slave flip-flip circuit (MS-FF) (100) includes master input transfer gate (108) connected to the input of a master latch portion (102) and a slave input transfer gate (110) connected to the input of a slave latch portion (104). A clock generating circuit (112) includes a first inverter (114-0) that provides an inverted clock signal CB1 and a second inverter (114-1) that provides a non-inverted clock signal C1. The clock signals C1 and CB1 are provided to the slave input transfer gate (104). The clock signals C1 and CB1 are further provided to the master input transfer gate (108) through clock lines (116-0) and (116-1) which have a parasitic resistances R1 and R2. The parasitic resistances R1 and R2 delay the C1 and CB1 signals and thereby provides a delayed inverted clock signal CB2 and a delayed non-inverted clock signal C2 to the master input transfer gate (108).Type: GrantFiled: May 20, 1999Date of Patent: June 5, 2001Assignee: NEC CorporationInventor: Hideaki Uemura
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Patent number: 6016003Abstract: In a semiconductor device, a lead frame includes normal leads terminating before an edge of a semiconductor chip and LOC leads extending over the semiconductor chip. The semiconductor chip is fixed to the lead frame by adhering the semiconductor chip to stitch sections of the LOC leads through an adhesive tape. A power supply pin and a ground pin are formed of LOC leads having a plurality of stitch sections, which are connected to a plurality of corresponding bonding pads, respectively, through bonding wires. On the other hand, signal pins are formed of normal leads which are connected to corresponding bonding pads through bonding wires, respectively.Type: GrantFiled: October 29, 1997Date of Patent: January 18, 2000Assignee: NEC CorporationInventor: Hideaki Uemura
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Patent number: 5436645Abstract: There is disclosed a laser beam output optical unit adjustment method and apparatus, which can perform inspection and adjustment of a laser beam unit and a laser scanning optical system including this unit used in a laser beam printer within a short period of time. The laser irradiation position is roughly adjusted using a wide-field position detector, and focus rough adjustment is then performed using a narrow-field position detector. Thereafter, fine adjustment of the irradiation position and focus fine adjustment are performed using the narrow-field position detector. An image enhancement tube capable of a high-speed gate operation is arranged in a laser scanning region, and instantaneously takes a beam spot during laser scanning. An image processing devices analyzes the taken spot image, and a calculation unit calculates various data.Type: GrantFiled: June 30, 1993Date of Patent: July 25, 1995Assignee: Canon Kabushiki KaishaInventors: Hideaki Uemura, Yozo Tobo, Fumio Ichikawa, Masatoshi Kato
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Patent number: 5351264Abstract: An optical apparatus (23) for emitting light is constituted by a fixation holder (8) fixed to a predetermined positioning fixation jig via a fixation plate (8a), a lens-barrel (10), fitted on a cylindrical portion of the fixation holder (8) via an annular gap (19), and formed of a transparent material, for holding a collimator lens (2), and a semi-conductor laser light source (1) fitted under pressure in the fixation holder (8). An ultraviolet curing adhesive (18) is uniformly filled in the gap (19). Before the ultraviolet curing adhesive (18) is cured, the lens-barrel (10) is movable in an optical axis direction (Z) and in two-dimensional directions (directions of arrows X and Y) on a plane perpendicular to the optical axis direction (Z) with respect to the fixation holder (8).Type: GrantFiled: February 11, 1993Date of Patent: September 27, 1994Assignee: Canon Kabushiki KaishaInventors: Masatoshi Kato, Yozo Tobo, Fumio Ichikawa, Jun Azuma, Hideaki Uemura
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Patent number: 5327252Abstract: A print evaluating apparatus includes an image reader having a plurality of photoreceptors to read a print pattern line by line; a relative movement causing device for imparting relative movement between the print pattern and the image reader in a direction different from a direction in which the photoreceptors are arranged; and a processor for effecting plural operations in parallel for plural evaluation items for image signals corresponding to the print pattern supplied by the image reader during the relative movement, and for effecting evaluation on data provided by the operations.Type: GrantFiled: September 23, 1991Date of Patent: July 5, 1994Assignee: Canon Kabushiki KaishaInventors: Shinsuke Tsuruoka, Hiroshi Haruyama, Hideaki Uemura