Patents by Inventor Hideaki Yoshimura
Hideaki Yoshimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150305157Abstract: A method of manufacturing a wiring board includes: forming an outer through hole in a core substrate; filling the outer through hole with an insulation resin; forming a first conductive layer on a surface of the insulation resin at a portion where a core connecting via is formed; forming a land around the first conductive layer; laminating the wiring layer on the core substrate after the forming of the first conductive layer and the forming of the land; forming an inner through hole having a smaller diameter than that of the outer through hole and penetrating through the core substrate and the wiring layer so as to penetrate through the insulation resin; and coating a first conductive film on an inner wall surface of the inner through hole, in which the core substrate and the first conductive film are electrically connected through the first conductive layer and the land.Type: ApplicationFiled: July 1, 2015Publication date: October 22, 2015Inventor: Hideaki YOSHIMURA
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Patent number: 9107314Abstract: A method of manufacturing a wiring board includes: forming an outer through hole in a core substrate; filling the outer through hole with an insulation resin; forming a first conductive layer on a surface of the insulation resin at a portion where a core connecting via is formed; forming a land around the first conductive layer; laminating the wiring layer on the core substrate after the forming of the first conductive layer and the forming of the land; forming an inner through hole having a smaller diameter than that of the outer through hole and penetrating through the core substrate and the wiring layer so as to penetrate through the insulation resin; and coating a first conductive film on an inner wall surface of the inner through hole, in which the core substrate and the first conductive film are electrically connected through the first conductive layer and the land.Type: GrantFiled: March 13, 2013Date of Patent: August 11, 2015Assignee: FUJITSU LIMITEDInventor: Hideaki Yoshimura
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Patent number: 8878076Abstract: A wiring substrate includes: a plate-like base material containing carbon fibers; a wiring layer formed on a surface of the base material; a first via including a first through hole penetrating through the base material, a first resin layer formed on an inner wall of the first through hole and including a second through hole, and a first conductive layer formed on an inner wall of the second through hole; and a second via including a third through hole penetrating through the base material and a second conductive layer formed on an inner wall of the third through hole, wherein an inside diameter of the third through hole is greater than an inside diameter of the second through hole.Type: GrantFiled: September 28, 2012Date of Patent: November 4, 2014Assignee: Fujitsu LimitedInventor: Hideaki Yoshimura
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COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, CONTROL METHOD OF COMMUNICATION APPARATUS AND PROGRAM
Publication number: 20140294009Abstract: There is provided a communication apparatus including a transmission source mapping algorithm acquisition unit configured to acquire an algorithm that assigns an external address and an external port number to an internal address and an internal port number of a transmission source, as a transmission source mapping algorithm, a destination mapping algorithm acquisition unit configured to acquire an algorithm that assigns an external address and an external port number to an internal address and an internal port number of a destination, as a destination mapping algorithm, and a generation unit configured to generate an external port number newly assigned to the internal address and the internal port number of the destination in a case where the transmission source mapping algorithm is more complicated than the destination mapping algorithm.Type: ApplicationFiled: March 12, 2014Publication date: October 2, 2014Applicant: Sony CorporationInventors: Yasunori Sahara, Kensuke Hatsukawa, Hiroshi Iwasaki, Takayuki Sugawara, Hideaki Yoshimura -
Patent number: 8800142Abstract: A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.Type: GrantFiled: February 8, 2011Date of Patent: August 12, 2014Assignee: Fujitsu LimitedInventors: Hnin Nway San Nang, Kazuya Arai, Kei Fukui, Shinpei Ikegami, Yasuhito Takahashi, Hideaki Yoshimura, Hitoshi Suzuki
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Patent number: 8754333Abstract: A printed circuit board includes a cell portion which includes cells having a plurality of through bores are arranged in a base material; and a base material portion which exists around an outer edge of the cell portion. The base material is formed of a prepreg, the prepreg includes a fiber material in which fiber threads are oriented in a first direction and in a second direction which is perpendicular to the first direction, and a resin material in which the fiber material is impregnated. The through bores are arranged along a third direction between the first direction and the second direction, wherein one side of the outer edges of the cell extends along the third direction.Type: GrantFiled: October 7, 2011Date of Patent: June 17, 2014Assignee: Fujitsu LimitedInventors: Hideaki Yoshimura, Kenji Iida, Yasutomo Maehara
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Patent number: 8669481Abstract: A laminated circuit board includes a first wiring board that has a first land formed on a surface thereof; a second wiring board that has a second land formed on a surface thereof; a bonding layer that is laid between the first wiring board and the second wiring board and electrically connects the first land and the second land via a conducting material; and a plate that has a through-hole through which the first land is connected to the second land, wherein a diameter of the through-hole of the plate is larger than a diameter of a component that is made by filling the conducting material.Type: GrantFiled: March 29, 2011Date of Patent: March 11, 2014Assignee: Fujitsu LimitedInventors: Hideaki Yoshimura, Asami Hondo
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Patent number: 8586876Abstract: A laminated circuit board includes a first wiring board that has a first land formed on a surface thereof; a second wiring board that has a second land formed on a surface thereof; a bonding layer that is made of a bonding resin, being laid between the first wiring board and the second wiring board, wherein the bonding layer electrically connects the first land and the second land via a conducting material; and a plate that has a through-hole into which the conducting material is supplied, wherein the plate has a resin accommodating space that accommodates therein an excess bonding resin that appears during layer stacking.Type: GrantFiled: April 13, 2011Date of Patent: November 19, 2013Assignee: Fujitsu LimitedInventor: Hideaki Yoshimura
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Publication number: 20130240259Abstract: A method of manufacturing a wiring board includes: forming an outer through hole in a core substrate; filling the outer through hole with an insulation resin; forming a first conductive layer on a surface of the insulation resin at a portion where a core connecting via is formed; forming a land around the first conductive layer; laminating the wiring layer on the core substrate after the forming of the first conductive layer and the forming of the land; forming an inner through hole having a smaller diameter than that of the outer through hole and penetrating through the core substrate and the wiring layer so as to penetrate through the insulation resin; and coating a first conductive film on an inner wall surface of the inner through hole, in which the core substrate and the first conductive film are electrically connected through the first conductive layer and the land.Type: ApplicationFiled: March 13, 2013Publication date: September 19, 2013Applicant: FUJITSU LIMITEDInventor: Hideaki YOSHIMURA
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Publication number: 20120325533Abstract: A method of manufacturing a multilayer circuit board includes forming a prepreg on a surface of a first circuit board including a first region in which a plated-through hole is formed and a second region in which a solid pattern is formed, the prepreg having a first hole reaching the plated-through hole and a second hole reaching the solid pattern, filling the first hole with a conductive paste, and pressing a second circuit board on the prepreg to laminate the first circuit board and the second circuit board to each other after filling the first hole with the conductive paste.Type: ApplicationFiled: April 23, 2012Publication date: December 27, 2012Applicant: FUJITSU LIMITEDInventor: Hideaki YOSHIMURA
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Publication number: 20120211270Abstract: A method of manufacturing a printed wiring board includes forming a first hole penetrating a base having conductivity, closing an opening of the first hole with a film, filling an insulating material into the first hole after closing the opening, removing the film after filling the insulating material, forming a plurality of second holes penetrating the insulating material, and forming a film having conductivity on an inner surface of each of the second holes to form a plurality of wirings penetrating the insulating material.Type: ApplicationFiled: February 17, 2012Publication date: August 23, 2012Applicant: FUJITSU LIMITEDInventor: Hideaki YOSHIMURA
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Publication number: 20120132464Abstract: A method for manufacturing a printed wiring board includes filling material in through holes formed in first lands on a first substrate, forming projection portions projecting from the first lands on the surface of the material of the through holes, placing a conductive material on the first lands, and electrically connecting the first lands of the first substrate and second lands of second substrate by pressing the conductive material under melting filled between the first and second lands in the lamination direction of the substrates by the projection portions when laminating the substrates in such a manner that the lands of the other substrate face the lands of the substrate for aggregation of the conductive material.Type: ApplicationFiled: November 16, 2011Publication date: May 31, 2012Applicant: FUJITSU LIMITEDInventors: Hideaki YOSHIMURA, Naohito MOTOOKA, Yasuhiro KARAHASHI, Asami HONDO, Satoshi YAMAGISHI, Hiromitsu KOBAYASHI
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Patent number: 8186053Abstract: A circuit board has plated through holes which are laid out with a fine pitch and meets requirements relating to characteristics such as strength and thermal expansion coefficient. A method of manufacturing a circuit board includes: a step of forming a core portion by thermal compression bonding prepregs formed by disposing carbon fibers so as to produce openings at positions where plated through holes will pass through and impregnating the carbon fibers with resin; a step of forming through holes that pass inside the openings at positions of the openings in the core portion; and a step of forming a conductive layer on inner surfaces of the through holes to form plated through holes at positions that do not interfere with the carbon fibers and thereby produce a core substrate.Type: GrantFiled: November 14, 2008Date of Patent: May 29, 2012Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.Inventors: Kishio Yokouchi, Hideaki Yoshimura, Katsuya Fukase
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Patent number: 8186052Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; filling the through-hole with an insulating material; performing electroless plating to coat the surface of the base member, in which the through-hole has been filled with the insulating material, with an electroless-plated layer; applying photo resist on the electroless-plated layer formed on the surface of the base member; optically exposing and developing the photo resist so as to form a resist pattern coating an end face of the through-hole filled with the insulating material; etching an electrically conductive layer formed on the surface of the base member with using the resist pattern as a mask; and removing the resist pattern coating the end face of the through-hole from the base member with using the electroless-plated layer as a release layer.Type: GrantFiled: July 15, 2008Date of Patent: May 29, 2012Assignee: Fujitsu LimitedInventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
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Publication number: 20120097442Abstract: A printed circuit board includes a cell portion which includes cells having a plurality of through bores are arranged in a base material; and a base material portion which exists around an outer edge of the cell portion. The base material is formed of a prepreg, the prepreg includes a fiber material in which fiber threads are oriented in a first direction and in a second direction which is perpendicular to the first direction, and a resin material in which the fiber material is impregnated. The through bores are arranged along a third direction between the first direction and the second direction, wherein one side of the outer edges of the cell extends along the third direction.Type: ApplicationFiled: October 7, 2011Publication date: April 26, 2012Applicant: Fujitsu LimitedInventors: Hideaki YOSHIMURA, Kenji Iida, Yasutomo Maehara
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Patent number: 8161636Abstract: A circuit board has plated through holes which are laid out with a fine pitch and meets requirements relating to characteristics such as the thermal expansion coefficient of the circuit board. A method of manufacturing a circuit board includes: a step of forming a core portion by thermal compression bonding prepregs which include first fibers that conduct electricity and second fibers that do not conduct electricity, which have the second fibers disposed at positions where plated through holes will pass through, and which are impregnated with resin; a step of forming through holes at positions in the core portion where the second fibers are disposed; and a step of forming a conductive layer on inner surfaces of the through holes to form plated through holes at positions that do not interfere with the first fibers and thereby produce a core substrate.Type: GrantFiled: November 17, 2008Date of Patent: April 24, 2012Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.Inventors: Kishio Yokouchi, Hideaki Yoshimura, Katsuya Fukase
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Patent number: 8153908Abstract: The circuit board is capable of tightly bonding a cable layer on a base member even if thermal expansion coefficients of the base member and the cable layer are significantly different. The circuit board comprises: the base member; and the cable layer being laminated on the base member with anchor patterns, which are electrically conductive layers formed on a surface of the base member.Type: GrantFiled: July 15, 2008Date of Patent: April 10, 2012Assignee: Fujitsu LimitedInventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
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Patent number: 8151456Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; plating the base member so as to coat an inner face of the through-hole with a plated layer; applying photo resist on the base member; optically exposing and developing the photo resist so as to form a resist pattern, which coats at least a planar area of the through-hole; and etching an electrically conductive layer formed on the surface of the base member. The resist pattern is formed so as to separate an area of exposing the conductive layer a prescribed distance away from an edge of the through-hole, and the prescribed length is longer than a distance of etching a side face of the conductive layer in the etching step.Type: GrantFiled: July 18, 2008Date of Patent: April 10, 2012Assignee: Fujitsu LimitedInventors: Yasutomo Maehara, Kenji Iida, Tomoyuki Abe, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
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Patent number: 8152953Abstract: The first support body is pressed against the second support body in response to the softening of the adhesive sheet. The fillers are allowed to reliably contact with one another between the first electrically-conductive land and the second electrically-conductive land. The fillers melt after the adhesive sheet has been softened. The intermetallic compounds are formed between the fillers and the electrically-conductive lands and between the fillers. Electrical connection is in this manner established between the first electrically-conductive land and the second electrically-conductive land. The matrix material and the adhesive sheet are then cured. The first support body and the second support body are firmly bonded to each other.Type: GrantFiled: February 4, 2009Date of Patent: April 10, 2012Assignee: Fujitsu LimitedInventors: Hideaki Yoshimura, Takashi Nakagawa, Kenji Fukuzono, Takashi Kanda, Tomohisa Yagi
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Publication number: 20120067635Abstract: A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.Type: ApplicationFiled: February 8, 2011Publication date: March 22, 2012Applicant: Fujitsu LimitedInventors: Hnin Nway San Nang, Kazuya Arai, Kei Fukui, Shinpei Ikegami, Yasuhito Takahashi, Hideaki Yoshimura, Hitoshi Suzuki