Patents by Inventor Hidebumi Ohnuki

Hidebumi Ohnuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5526564
    Abstract: A multilayered printed wiring board includes a plurality of inner layer circuits, ground layers, first insulating layers, a second insulating layer, a surface layer circuit, and a parts mounting pad. The inner layer circuits are arranged parallel to each other in a flat manner in at least one inner layer. The ground layers are formed on and under the inner layer circuits to sandwich the inner layer circuits. The first insulating layers are respectively formed between the ground layers and the inner layer circuits to insulate the inner layer circuits from each other and the inner layer circuits from the ground layers. The second insulating layer is formed at least on an uppermost one of the ground layers and serving as a surface layer. The surface layer circuit is selectively formed on the second insulating layer.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: June 18, 1996
    Assignee: NEC Corporation
    Inventors: Tutomu Ohshima, Hidebumi Ohnuki, Ryo Maniwa
  • Patent number: 5480675
    Abstract: An apparatus for plating a printed circuit board including a non-through hole for connecting between a surface conductive layer and an interlayer wiring layer has a jig, a vessel, a supporting body carrying the jig for causing it to vibrate and swing in a plating liquid contained in the vessel, and a vacuum pump connected to the vessel for exhausting the air in the vessel thereby enhancing removal of bubbles in the non-through hole. A method of plating a printed circuit board includes the step of reducing the pressure inside the vessel simultaneously with the printed circuit board being subjected to the vibration and swinging actions thereby to remove a bubble existing inside the non-through hole. The removal of the bubble makes it possible to have a uniform plating film formed in an inner wall of the non-through hole and ensures the reliable electric connection to be established through the non-through hole between a surface conductive layer and interlayer conductive layers.
    Type: Grant
    Filed: March 10, 1994
    Date of Patent: January 2, 1996
    Assignee: NEC Corporation
    Inventors: Tomoo Murakami, Hidebumi Ohnuki, Takanori Tsunoda, Ryo Maniwa
  • Patent number: 5455393
    Abstract: A multilayered printed wiring board includes a plurality of inner layer circuits, ground layers, first insulating layers, a second insulating layer, a surface layer circuit, and a parts mounting pad. The inner layer circuits are arranged parallel to each other in a flat manner in at least one inner layer. The ground layers are formed on and under the inner layer circuits to sandwich the inner layer circuits. The first insulating layers are respectively formed between the ground layers and the inner layer circuits to insulate the inner layer circuits from each other and the inner layer circuits from the ground layers. The second insulating layer is formed at least on an uppermost one of the ground layers and serving as a surface layer. The surface layer circuit is selectively formed on the second insulating layer.
    Type: Grant
    Filed: November 30, 1993
    Date of Patent: October 3, 1995
    Assignee: NEC Corporation
    Inventors: Tutomu Ohshima, Hidebumi Ohnuki, Ryo Maniwa
  • Patent number: 5218761
    Abstract: A laminated board in which each of prepreg sheets is sandwiched between an internal printed wiring board which is provided with wirings and each of external printed wiring board which is provided with wirings on the outermost surface thereof is formed with through-holes by drilling. A thin copper plating layer is formed on the surfaces of the laminated board including the inner wall of the through-hole. Then, an alkali-soluble photoresist film is selectively formed on the surface of the thin copper plating layer and a thick copper plating layer is formed. The thin copper plating layer is removed by using the thick copper plating layer as a mask to forme through holes and wirings. The through holes and wirings can be thus formed without using the additive process. Environmental pollution due to use of organic solvents can be prevented by avoiding the use of an organic solvent-soluble resist film having a strong resistance to alkalis.
    Type: Grant
    Filed: April 8, 1992
    Date of Patent: June 15, 1993
    Assignee: NEC Corporation
    Inventors: Ryo Maniwa, Hidebumi Ohnuki
  • Patent number: 5030373
    Abstract: An aqueous solution containing 0.1 g/l or more of piperidine or a derivative, 100-500 g/l of sulfuric acid, 10-50 g/l of hydrogen peroxide and 0.5 g/l or more of phosphoric acid is used for treating the surface of copper or copper alloy used in manufacturing of printed circuit.
    Type: Grant
    Filed: March 8, 1990
    Date of Patent: July 9, 1991
    Assignee: Tokai Denka Kogyo Kabushiki Kaisha
    Inventors: Toshiya Kimura, Koichi Wakashima, Hidebumi Ohnuki, Shigeki Nakajima, Katsutoshi Itani, Akira Hirai
  • Patent number: 4668332
    Abstract: A multi-layer printed wiring board in which an internal board has a wiring pattern on both sides. Two conductive plates for establishing respective voltage planes are formed with a pattern of grooves to match the wiring pattern of the internal board. The internal board is then sandwiched to the two sides of the conductive plates, with the grooves registering with the wiring pattern, and with intermediate insulating layers. Further, insulated wiring patterns are formed on the exterior sides of the conductive plates together with through-holes through the assembly.
    Type: Grant
    Filed: April 26, 1985
    Date of Patent: May 26, 1987
    Assignee: NEC Corporation
    Inventors: Hidebumi Ohnuki, Toshiaki Asano, Takashi Atarashi, Sunao Yasui