Patents by Inventor Hidechika Kishigami

Hidechika Kishigami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5613078
    Abstract: A microprocessor having a data-width change function has a core section in the microprocessor for fetching an instruction from the external memories in instruction fetch request, transferring data between the external memories and the microprocessor in data access request, and executing the instruction fetched and processing operand access operation, internal buses connected to the core section for transferring data to the core section, a memory for storing first bus indication data and second bus-width indication data indicating a bus-width of specified external buses, a bus-width change circuit connected to the internal buses and the external buses for changing specified external buses in the external buses to connect specified buses in the internal buses to be used during the instruction fetch bus cycle and the data access bus cycle, and a bus-width change controller connected to the bus change circuit and the memory for changing the bus-width of the buses in the external data buses based on the first bus-
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: March 18, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidechika Kishigami
  • Patent number: 5155817
    Abstract: A microprocessor employs pipelined architecture and comprises a first execution processor for executing and processing a first kind of instructions among decoded instructions according to microprogram control, a second execution processor for executing and processing a second kind of instructions which are different from the first kind of instructions according to hardwired control, and a controller. The controller issues decoded instructions in a program sequence, selectively determines for each of the decoded instructions which of the first and second execution processors shall execute and process an instruction, and operates the first and second execution processors independently of each other and in parallel with each other.
    Type: Grant
    Filed: April 3, 1989
    Date of Patent: October 13, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidechika Kishigami, Misao Miyata
  • Patent number: 4807175
    Abstract: In Booth's method of calculating a product of a multiplicand X and a multiplier Y, Y is divided into plural partial multipliers PP.sub.i (Y.sub.i, Y.sub.i+1, Y.sub.i+2); partial products PD.sub.i are formed separately in sequence by multiplying X by each of decoded partial multiplier values V.sub.pp decoded in accordance with Booth theory; and all the partial products PD.sub.i are accumulatively added to obtain the product. To increase the processing speed twice in spite of a relatively simple circuit configuration, two partial products of X and V.sub.pp are formed simultaneously in sequence and added to obtain a partial product sum PS.sub.i, and all the two partial product sums are accumulatively added to obtain a final result.
    Type: Grant
    Filed: March 6, 1987
    Date of Patent: February 21, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeji Tokumaru, Hidechika Kishigami