Patents by Inventor Hidechika Kumamoto

Hidechika Kumamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7583402
    Abstract: This image forming device 1 comprises an image processing unit 9, an HDD 23 and an image forming unit. The image processing unit 9 is capable of instructing the output of the image data sent from the PC 43. The HDD 23 is connected to the image processing unit 9 and is capable of storing the image data to be delivered. The image forming unit is capable of receiving the instruction from the image processing unit 9 and delivering onto paper or the like the image data stored in the HDD 23. Then, when the ID information contained in the image data is detected by the image processing unit 9, writing of image data to the HDD 23 is prohibited.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: September 1, 2009
    Assignee: Kyocera Mita Corporation
    Inventors: Katsuyuki Teranishi, Hidechika Kumamoto
  • Patent number: 7548337
    Abstract: This image forming device 1 comprises a control unit, a connector interface 31, an external memory 33, and an image forming unit. The control unit instructs the output of a predetermined image data. The connector interface 31 is connected to the control unit. The external memory 14 can be removably connected to the connector interface 31 while it stores the output image data. The image forming unit is capable of receiving the instruction from the control unit and delivering onto paper the image data stored in the external memory 14.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: June 16, 2009
    Assignee: Kyocera Mita Corporation
    Inventors: Katsuyuki Teranishi, Hidechika Kumamoto
  • Publication number: 20070097433
    Abstract: This image forming device 1 comprises a control unit, a connector interface 31, an external memory 33, and an image forming unit. The control unit instructs the output of a predetermined image data. The connector interface 31 is connected to the control unit. The external memory 14 can be removably connected to the connector interface 31 while it stores the output image data. The image forming unit is capable of receiving the instruction from the control unit and delivering onto paper the image data stored in the external memory 14.
    Type: Application
    Filed: October 27, 2005
    Publication date: May 3, 2007
    Inventors: Katsuyuki Teranishi, Hidechika Kumamoto
  • Publication number: 20070097432
    Abstract: This image forming device 1 comprises an image processing unit 9, an HDD 23 and an image forming unit. The image processing unit 9 is capable of instructing the output of the image data sent from the PC 43. The HDD 23 is connected to the image processing unit 9 and is capable of storing the image data to be delivered. The image forming unit is capable of receiving the instruction from the image processing unit 9 and delivering onto paper or the like the image data stored in the HDD 23. Then, when the ID information contained in the image data is detected by the image processing unit 9, writing of image data to the HDD 23 is prohibited.
    Type: Application
    Filed: October 27, 2005
    Publication date: May 3, 2007
    Inventors: Katsuyuki Teranishi, Hidechika Kumamoto
  • Patent number: 6049635
    Abstract: An apparatus for and a method of reliably detecting a very small dotted image area. A detecting area including a predetermined number of pixels including a target pixel is set. It is judged whether or not the detecting area belongs to a dotted image area on the basis of the number of edge pixels in the detecting area. Consequently, it is possible to detect edges peculiar to the dotted image area on the basis of a leading edge portion or a trailing edge portion of the density, to detect the very small dotted image area on the basis of the number of edge pixels.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: April 11, 2000
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Shinji Hayashi, Masaya Fujimoto, Hidechika Kumamoto
  • Patent number: 5878162
    Abstract: An image processing circuit which adds, by means of a yellow color image data, forgery tracing information to yellow, magenta and cyan color image data obtained by reading out of an original. A tracing information adder replaces the read-out yellow color image data with a yellow color image of a higher density in a low-density area where the density of the read-out yellow color image data is equal to or below a set threshold value. In a high-density area where the density of the read-out yellow color image data exceeds the set threshold value, the tracing information is added by adding a predetermined value to the read-out yellow color image data.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: March 2, 1999
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Tadashi Miyazaki, Hidechika Kumamoto
  • Patent number: 5771313
    Abstract: An apparatus for and a method of detecting a dotted image area in an image. It is judged on the basis of image data corresponding to pixels in a first judging area which includes a predetermined number of pixels including a target pixel whether or not the target pixel is a peculiar point pixel (a peak pixel or a dip pixel). Further, it is judged on the basis of image data corresponding to pixels in a second judging area which is larger than the first judging area whether or not the target pixel is a peculiar point pixel. The dotted image area in the image is detected on the basis of the results of judgment related to the first judging area and the second judging area.
    Type: Grant
    Filed: November 2, 1995
    Date of Patent: June 23, 1998
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Shinji Hayashi, Masaya Fujimoto, Hidechika Kumamoto
  • Patent number: 5754312
    Abstract: Disclosed is an apparatus for detecting pixels in a dotted image area (dotted area pixels). Image data corresponding to each of the pixels is coded into one of a predetermined number of discrete values. The distance between change points at which the value of the pixel after the coding is changed from a first value to a second value is detected. Further, it is examined whether or not periodicity is recognized in the distance between the change points in the vicinity of a target pixel. If periodicity is recognized in the distance between the change points, it is judged that the target pixel may constitute a dotted image area.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: May 19, 1998
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Masaya Fujimoto, Haruo Yamamoto, Masayuki Mizuno, Hidechika Kumamoto, Shinji Hayashi
  • Patent number: 5754708
    Abstract: An apparatus for and a method of reliably detecting a very small dotted image area. A detecting area including a predetermined number of pixels including a target pixel is set. It is judged whether or not the detecting area belongs to a dotted image area on the basis of the number of edge pixels in the detecting area. Consequently, it is possible to detect edges peculiar to the dotted image area on the basis of a leading edge portion or a trailing edge portion of the density, to detect the very small dotted image area on the basis of the number of edge pixels.
    Type: Grant
    Filed: November 2, 1995
    Date of Patent: May 19, 1998
    Assignee: Mita Industrial Co. Ltd.
    Inventors: Shinji Hayashi, Masaya Fujimoto, Hidechika Kumamoto
  • Patent number: 5729627
    Abstract: An apparatus for and a method of judging a dotted image area using a small-capacity memory. Image data corresponding to one line out of image data representing an original image are stored in a line memory. On the line corresponding to the image data stored in the line memory, a target pixel is successively set along the main scanning direction. Image data corresponding to the target pixel is compared with image data corresponding to pixels around the target pixel. It is judged whether or not the target pixel is a peculiar point pixel on the basis of the result of the comparison. Further, the distance between peculiar point pixels is operated. The operated distance between the peculiar point pixels is referred to a predetermined judgment basis, to judge whether or not a judging area including the finite number of pixels is a dotted image area.
    Type: Grant
    Filed: November 2, 1995
    Date of Patent: March 17, 1998
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Masayuki Mizuno, Masaya Fujimoto, Haruo Yamamoto, Hidechika Kumamoto
  • Patent number: 5712924
    Abstract: A color image is by an optical scanner for conversion into three primary color data corresponding to the respective densities of the three primary colors. An edge detector detects a pixel of an edge based on the three primary color data. A pixel color judging device judges a color of a target pixel based on the three primary color data of the target pixel and its adjacent pixels. Based on edge detection results of the edge detector and pixel color judgment results of the pixel color judging device, detected is a pixel of a black edge. Judgement conditions for the pixel color judgement are established based upon characteristics that depend upon the order of arrangement of color filters in a scanner.
    Type: Grant
    Filed: October 31, 1995
    Date of Patent: January 27, 1998
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Masaya Fujimoto, Haruo Yamamoto, Tadashi Miyazaki, Hidechika Kumamoto, Shinji Hayashi
  • Patent number: 5684600
    Abstract: An image processor performs emphasis processings suitable for materials to be copied to produce clear copy outputs. The image processor has a digitizing circuit which outputs a digital signal produced by digitizing an image. The processor further has a first detecting circuit which detects an area of the digital signal including a periodic component, a second detecting circuit which detects a character area of the digital signal, and a smoothing circuit which smoothes the digital signal to output a smoothed signal. Either the digital signal or the smoothed signal is selected and outputted by a changeover circuit according to an output of the first detecting circuit. The output of the changeover circuit is differentiated into a plurality of differentiated signals by a differentiating circuit by use of a plurality of different coefficients. One of the differentiated signals is selected and outputted according to the outputs of the first and second detecting circuits.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: November 4, 1997
    Assignee: Mita Industrial Co.,Ltd.
    Inventors: Tadashi Miyazaki, Masaya Fujimoto, Hidechika Kumamoto, Haruo Yamamoto, Shinji Hayashi
  • Patent number: 5519500
    Abstract: A synchronization signal generating circuit generates a synchronization signal used to output read data sequentially in a specified period. This circuit is provided with a clock generator means for generating a reference clock, a first counter unit for counting the reference clock; a synchronization signal generator for generating the synchronization signal in a first period in accordance with a count value of the first counter unit; a second counter unit for counting the generation of the synchronization signal; a resetter for resetting the second counter unit when a count value of the second counter unit reaches a specified value; and a period changer for controlling the synchronization signal generator so as to generate the synchronization signal in a second period only when the count value of the second counter unit reaches the specified value.
    Type: Grant
    Filed: May 14, 1993
    Date of Patent: May 21, 1996
    Assignee: Mita Industrial Co., Ltd.
    Inventor: Hidechika Kumamoto
  • Patent number: 5418896
    Abstract: A skew processing circuit 33 includes two line buffers, a skew processing type line buffer 331 and an original type line buffer 332, and a write/read control circuit 333 for controlling the two line buffers. The write/read control circuit 333 is a control circuit for writing a given image data in the line buffers 331, 332 in single lines and selectively reading the data written in the two line buffers 331, 332. When an image data is written in the original type line buffer 332, addressed are sequentially written from the head address 0. On the other hand, when the image data is written in the skew processing type line buffer 331, a write start address RH0 is determined in correspondence with a skew angle, and the write start address RH0 is shifted in each line to discard the head portion of the image data by specified dots (specified addresses).
    Type: Grant
    Filed: March 14, 1991
    Date of Patent: May 23, 1995
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Hidechika Kumamoto, Haruo Yamamoto, Masaya Fujimoto, Tsukasa Matsushita
  • Patent number: 5272546
    Abstract: A laser beam controller comprises a basic pulse signal generating circuit, a delay circuit, a delay control circuit, a pulse generating circuit and a laser beam generator. The basic pulse signal generating circuit generates periodically occurring basic pulse signal. The delay circuit delays the basic pulse signal. The delay control circuit controls the delay time of the basic pulse in the delay circuit according to image data. The pulse generating circuit generates an output pulse having a width corresponding to the delay time of the basic pulse signal. The laser beam generator generates a laser beam for a duration corresponding to the width of the output pulse by said pulse generating circuit. According to the controller, any desired gradation of a pixel of the image is desirably produced.
    Type: Grant
    Filed: March 4, 1991
    Date of Patent: December 21, 1993
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Haruo Yamamoto, Akira Shimatani, Hidechika Kumamoto, Masaya Fujimoto, Tsukasa Matsushita
  • Patent number: 5083217
    Abstract: A shadow-added image formation device includes a photoelectric converting mechanism for converting every pixel into an electric signal, A/D-converting mechanism for A/D-converting an output of the photoelectric converting mechanism, a signal converting mechanism for converting an output of the A/D-converting mechanism into a binary serial signal representing white and black pixels, and a detecting mechanism for detecting an area to which shadow can be added from the output of the signal converting mechanism. A shadow signal formation mechanism for outputting a signal, a setting mechanism for setting a shadow area, an adding mechanism for comparing the widths of the areas detected by the detecting mechanism and set by the setting mechanism and adding the shadow signal to the binary serial signal corresponding to the smaller one of the areas determined by the comparison, and a reproducing mechanism for reproducing an image to which the shadow signal has been added, are also provided.
    Type: Grant
    Filed: June 19, 1990
    Date of Patent: January 21, 1992
    Assignee: Mita Industrial Co., Ltd.
    Inventor: Hidechika Kumamoto
  • Patent number: 5072310
    Abstract: An integrated circuit (IC) card for use in an image processing machine, such as a digital copying machine. The IC card includes a first storage area for storing data for controlling said image processor and a second storage area for storing image data to be processed by said image processor.
    Type: Grant
    Filed: May 14, 1990
    Date of Patent: December 10, 1991
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Haruo Yamamoto, Tsukasa Matsushita, Hidechika Kumamoto, Masaya Fujimoto
  • Patent number: 5070412
    Abstract: An enlargement/reduction signal generating apparatus comprises means for generating basic clock pulses, means for generating frequency-divided clock pulses of different kinds, having the different frequencies by dividing the frequency of said basic clock pulses, means for generating selection signals to combine said clock pulses generated by said basic clock pulse generating means and said frequency-divided clock pulse generating means, whereby the ratio of said reading clock pulses to said writing clock pulses corresponds to a predetermined enlargement/reduction ratio, and means for making enlargement/reduction clock pulses by combining said basic clock pulses and said frequency-divided clock pulses in correspondence with said selection signals from said selection signal generating means and for outputting said enlargement/reduction clock pulses as said reading clock pulses or said writing clock pulses.
    Type: Grant
    Filed: November 27, 1989
    Date of Patent: December 3, 1991
    Assignee: Mita Indusatrial Co., Ltd.
    Inventors: Hidechika Kumamoto, Tsukasa Matsushita
  • Patent number: 5016194
    Abstract: In an image forming apparatus including a digital image processing device, an overlay memory stores predetermined image data. The image data stored in the overlay memory is read at a predetermined timing in a predetermined cycle and composite data is made from the image data and image data outputted from a line memory. Since the image data stored in the overlay memory is read at the predetermined timing in the predetermined cycle, various kinds of overlaid image which may include a space-magnified image can be made by arbitrarily selecting the timing and cycle for reading.
    Type: Grant
    Filed: November 6, 1989
    Date of Patent: May 14, 1991
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Tsukasa Matsushita, Hidechika Kumamoto
  • Patent number: 4812881
    Abstract: An automatic image-density control system for photo-copying the page-to-page content of an open book, in which optimum values (of exposure or development bias) needed for precisely copying the page-to-page content are initially established by performing either continuous pre-scanning of both pages of an open book or pre-scanning of the second page after completing photo-copying of the first page, and then, based on the optimum values thus established in conjunction with the first page content, photo-copying operation for the first page content is executed, and then, based on the optimum values established for the second-page content, photo-copying operation is sequentially executed for the second-page content.
    Type: Grant
    Filed: January 27, 1987
    Date of Patent: March 14, 1989
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Hidechika Kumamoto, Satoshi Kuroyanagi, Setsuo Hori