Patents by Inventor Hidefumi Kobayashi

Hidefumi Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11726680
    Abstract: A storage control device of controlling a storage device includes memory; and processor circuitry coupled to the memory, the processor circuitry being configured to perform processing, the processing including: determining a mode that indicates how to back up configuration information of the storage device on a basis of a redundant configuration state with another storage control device; and backing up the configuration information from a memory to a backup device on a basis of the determined mode.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: August 15, 2023
    Assignee: FUJITSU LIMITED
    Inventor: Hidefumi Kobayashi
  • Publication number: 20220027068
    Abstract: A storage control device of controlling a storage device includes memory; and processor circuitry coupled to the memory, the processor circuitry being configured to perform processing, the processing including: determining a mode that indicates how to back up configuration information of the storage device on a basis of a redundant configuration state with another storage control device; and backing up the configuration information from a memory to a backup device on a basis of the determined mode.
    Type: Application
    Filed: April 2, 2021
    Publication date: January 27, 2022
    Applicant: FUJITSU LIMITED
    Inventor: Hidefumi KOBAYASHI
  • Patent number: 10234929
    Abstract: A first control apparatus includes a first memory unit including a local cache, a first power supply that supplies electric power to the first memory unit, and a control unit. The control unit controls a write into a memory device by a write-back method, using the local cache. The control unit mirrors data of the local cache in a mirror cache of a second control apparatus. The control unit determines whether the mirror cache is included in a second memory unit that receives electric power from a second power supply of the second control apparatus, upon detecting an abnormal state of a battery for supplying electric power to the second memory unit in case of power outage of the second power supply. The second memory unit switches write control for the memory device to a write-through method, when the second memory unit includes the mirror cache.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Hidefumi Kobayashi, Satoshi Yazawa, Atsushi Igashira, Wataru Iizuka, Motohiro Sakai, Akihito Kobayashi, Shinichiro Matsumura, Kenji Kobayashi
  • Patent number: 9916242
    Abstract: A storage system includes control devices and a second processor. The second processor determines a number of abnormal batteries when an abnormality has occurred in a first battery. The second processor assigns a second cache currently assigned to a second control device associated with the first battery to a first control device when the number is smaller than a threshold. The second processor assigns a mirror cache currently assigned to the second control device to a third control device when the number is smaller than the threshold. The second processor instructs the first control device to control write to a first storage device associated with a first cache by using the first cache. Data of the first cache is mirrored to the mirror cache. The second processor instructs the first control device to control write to a second storage device associated with the second cache by using the second cache.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: March 13, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Yasuhiro Ogasawara, Hidetoshi Nishi, Shigeru Akiyama, Tsukasa Matsuda, Tatsuya Yanagisawa, Hidefumi Kobayashi, Satoshi Yazawa, Atsushi Igashira, Wataru Iizuka
  • Patent number: 9703695
    Abstract: A control device including a processor. The processor configured to allocate a data area of a memory device to a plurality of memory areas of data blocks of a first size; allocate identical data blocks of the first size to a plurality of the data areas of the memory device; manage management information indicating a data storing state of the plurality of memory areas of data blocks of the first size in each data area; determine, based on the management information regarding a plurality of data areas allocated with respect to a data block to be written, one data area from the plurality of data areas; and generate write data of a second size, which is different from the first size, including data of the data block to be written and write the write data in the one data area.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: July 11, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hidefumi Kobayashi, Yoshihito Konta, Atsushi Igashira, Koutarou Nimura, Marie Abe, Mihoko Tojo, Masatoshi Nakamura
  • Publication number: 20170132129
    Abstract: A storage system includes control devices and a second processor. The second processor determines a number of abnormal batteries when an abnormality has occurred in a first battery. The second processor assigns a second cache currently assigned to a second control device associated with the first battery to a first control device when the number is smaller than a threshold. The second processor assigns a mirror cache currently assigned to the second control device to a third control device when the number is smaller than the threshold. The second processor instructs the first control device to control write to a first storage device associated with a first cache by using the first cache. Data of the first cache is mirrored to the mirror cache. The second processor instructs the first control device to control write to a second storage device associated with the second cache by using the second cache.
    Type: Application
    Filed: October 27, 2016
    Publication date: May 11, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Yasuhiro Ogasawara, Hidetoshi Nishi, Shigeru Akiyama, Tsukasa Matsuda, Tatsuya Yanagisawa, Hidefumi Kobayashi, Satoshi Yazawa, Atsushi Igashira, Wataru Iizuka
  • Patent number: 9529707
    Abstract: Write commands for a storage device specify write data with either a first data step size or a second data step size. In the former case, the storage device performs a read-modify-write (RMW) cycle which includes reading data with the second data step size. In the latter case, the storage device executes the command in a single write cycle. A command sorting unit sorts received commands into two groups, first commands and second commands, when storing them in a memory. First commands are write commands whose data boundaries do not match with the second data step size. Second commands include write commands whose data boundaries match with the second data step size. A command issuing unit converts first commands into a second command upon predetermined conditions. The command issuing unit issues the second commands to the storage device, in preference to the first commands.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: December 27, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Masatoshi Nakamura, Koutarou Nimura, Marie Abe, Yoshihito Konta, Hidefumi Kobayashi, Mihoko Tojo, Yasuhiro Ogasawara, Shigeru Akiyama
  • Publication number: 20160321175
    Abstract: A first control apparatus includes a first memory unit including a local cache, a first power supply that supplies electric power to the first memory unit, and a control unit. The control unit controls a write into a memory device by a write-back method, using the local cache. The control unit mirrors data of the local cache in a mirror cache of a second control apparatus. The control unit determines whether the mirror cache is included in a second memory unit that receives electric power from a second power supply of the second control apparatus, upon detecting an abnormal state of a battery for supplying electric power to the second memory unit in case of power outage of the second power supply. The second memory unit switches write control for the memory device to a write-through method, when the second memory unit includes the mirror cache.
    Type: Application
    Filed: March 23, 2016
    Publication date: November 3, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Hidefumi Kobayashi, SATOSHI YAZAWA, Atsushi IGASHIRA, Wataru Iizuka, Motohiro Sakai, Akihito Kobayashi, Shinichiro Matsumura, Kenji KOBAYASHI
  • Patent number: 9244773
    Abstract: An information processing apparatus that performs a startup control of redundantly configured modules includes a memory to retain abnormality information regarding an abnormality that occurs at time of startup control of the modules, and a startup controller section executing a startup process by sequentially executing the process, generating the abnormality information, determining whether a reduced operation is possible or not when the module in which an abnormality occurs at the time of startup control is detected, completing an execution of the process block in progress when it is determined that the reduced operation is possible, executing a restart process on a module selected from all the modules in which abnormalities occur at the time of startup control based on the abnormality information and completing an execution of the process block in progress after completing the restart process when determined that the reduced operation is not possible.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: January 26, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hidefumi Kobayashi, Tatsuya Yanagisawa
  • Patent number: 9195529
    Abstract: An information processing apparatus manages activation of a program by a task which is a unit of execution, and executes a task for each sequence in units of process block. The information processing apparatus has a nonvolatile memory which keeps an execution state management table. The execution state of the process block is stored in the execution state management table. The control unit performs a first activation procedure which initializes the execution state management table and, while updating the execution state in the execution state management table, executes the task. When activation by the first activation procedure has failed, the control unit performs activation by a second activation procedure and identifies a suspicious sequence. When activation by the second activation procedure has failed, the control unit performs activation by a third activation procedure and identifies a suspicious task.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 24, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Yuusuke Oota, Hidefumi Kobayashi, Tatsuya Yanagisawa, Mihoko Tojo, Tsukasa Makino
  • Publication number: 20150324301
    Abstract: A storage unit stores a first control program that includes an encryption program and version information indicating the version number of the encryption program. When backing up configuration data, an operation unit stores encrypted data obtained by encrypting the configuration data, a first part of the encryption program used for the encryption, and the version information in a non-volatile storage medium. After the first control program is updated to a second control program, the operation unit obtains a second part of the encryption program corresponding to the version number registered in the non-volatile storage medium from the second control program, and then generates the encryption program to be used for decrypting the encrypted data stored in the non-volatile storage medium, using the second part and the first part stored in the non-volatile storage medium.
    Type: Application
    Filed: April 20, 2015
    Publication date: November 12, 2015
    Inventors: Wataru Iizuka, Hidefumi Kobayashi, Yuusuke Oota, Atsushi IGASHIRA
  • Publication number: 20150121021
    Abstract: Write commands for a storage device specify write data with either a first data step size or a second data step size. In the former case, the storage device performs a read-modify-write (RMW) cycle which includes reading data with the second data step size. In the latter case, the storage device executes the command in a single write cycle. A command sorting unit sorts received commands into two groups, first commands and second commands, when storing them in a memory. First commands are write commands whose data boundaries do not match with the second data step size. Second commands include write commands whose data boundaries match with the second data step size. A command issuing unit converts first commands into a second command upon predetermined conditions. The command issuing unit issues the second commands to the storage device, in preference to the first commands.
    Type: Application
    Filed: October 9, 2014
    Publication date: April 30, 2015
    Inventors: Masatoshi Nakamura, Koutarou Nimura, Marie Abe, Yoshihito Konta, Hidefumi Kobayashi, Mihoko Tojo, Yasuhiro Ogasawara, Shigeru Akiyama
  • Publication number: 20140289493
    Abstract: A control device including a processor. The processor configured to allocate a data area of a memory device to a plurality of memory areas of data blocks of a first size; allocate identical data blocks of the first size to a plurality of the data areas of the memory device; manage management information indicating a data storing state of the plurality of memory areas of data blocks of the first size in each data area; determine, based on the management information regarding a plurality of data areas allocated with respect to a data block to be written, one data area from the plurality of data areas; and generate write data of a second size, which is different from the first size, including data of the data block to be written and write the write data in the one data area.
    Type: Application
    Filed: February 3, 2014
    Publication date: September 25, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Hidefumi Kobayashi, Yoshihito Konta, Atsushi Igashira, Koutarou Nimura, Marie Abe, Mihoko Tojo, Masatoshi Nakamura
  • Patent number: 8762648
    Abstract: In a storage system, a first reboot controller in a first control apparatus causes a second control apparatus to reboot, when it is detected that a second control apparatus has stopped access operations. The first reboot controller also places a boot event record in a non-volatile storage device of the second control apparatus to indicate that the rebooting of the second control apparatus has been caused by the first control apparatus. After that, a second reboot controller in the second control apparatus causes at least the first control apparatus to reboot while keeping intact the cache data stored in a cache memory of the first control apparatus, when the access controller of the first control apparatus is stopped while the second control apparatus is rebooted, and when a boot event record is found in the non-volatile storage device of the second control apparatus.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: June 24, 2014
    Assignee: Fujitsu Limited
    Inventors: Kazuo Nakashima, Minoru Muramatsu, Hidefumi Kobayashi
  • Publication number: 20140173337
    Abstract: A storage-apparatus has a plurality of storage-devices and a controller for controlling data read from and write to the plurality of storage-devices, the controller includes a determination-unit and a restore-processing-unit, when a new storage-device has failed in a non-redundant state being a redundant group state without redundancy, in which some of the storage-devices had failed out of the plurality of storage-devices, the determination-unit configured to determine whether execution of compulsory restore of the redundant group is possible or not on the basis of a failure cause of the plurality of failed storage-devices, and if the determination unit determines that the execution of compulsory restore of the redundant group is possible, the restore-processing-unit configured to incorporate a plurality of storage-devices including a newly failed storage-device in the non-redundant state into the redundant group and to compulsorily restore the storage-apparatus to an available state.
    Type: Application
    Filed: November 6, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Atsushi IGASHIRA, Hidefumi KOBAYASHI
  • Publication number: 20140140135
    Abstract: A storage device includes a control device that controls an access to storage, a volatile memory that stores data that is used for operation control of the control device, and a non-volatile memory is a backup destination of the data. Furthermore a storage device includes a detection unit that detects a failure occurred in the control device, a determination unit that determines whether or not backup data that is stored in the non-volatile memory is valid when the detection unit detects the failure occurred in the control device, and a control unit that causes the control device to execute a first processing of restoring the backup data of the non-volatile memory in the volatile memory after restart-up without backup of the data of the volatile memory, when the determination unit determines that the backup data of the non-volatile memory is valid.
    Type: Application
    Filed: October 7, 2013
    Publication date: May 22, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Reina Okano, Hidefumi Kobayashi, Tatsuya Yanagisawa, Wataru Iizuka
  • Publication number: 20140095921
    Abstract: An information processing apparatus that performs a startup control of redundantly configured modules includes a memory to retain abnormality information regarding an abnormality that occurs at time of startup control of the modules, and a startup controller section executing a startup process by sequentially executing the process, generating the abnormality information, determining whether a reduced operation is possible or not when the module in which an abnormality occurs at the time of startup control is detected, completing an execution of the process block in progress when it is determined that the reduced operation is possible, executing a restart process on a module selected from all the modules in which abnormalities occur at the time of startup control based on the abnormality information and completing an execution of the process block in progress after completing the restart process when determined that the reduced operation is not possible.
    Type: Application
    Filed: September 23, 2013
    Publication date: April 3, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Hidefumi Kobayashi, Tatsuya Yanagisawa
  • Publication number: 20140059335
    Abstract: An information processing apparatus manages activation of a program by a task which is a unit of execution, and executes a task for each sequence in units of process block. The information processing apparatus has a nonvolatile memory which keeps an execution state management table. The execution state of the process block is stored in the execution state management table. The control unit performs a first activation procedure which initializes the execution state management table and, while updating the execution state in the execution state management table, executes the task. When activation by the first activation procedure has failed, the control unit performs activation by a second activation procedure and identifies a suspicious sequence. When activation by the second activation procedure has failed, the control unit performs activation by a third activation procedure and identifies a suspicious task.
    Type: Application
    Filed: July 12, 2013
    Publication date: February 27, 2014
    Inventors: Yuusuke Oota, Hidefumi Kobayashi, TATSUYA YANAGISAWA, Mihoko Tojo, Tsukasa Makino
  • Publication number: 20120054441
    Abstract: In a storage system, a first reboot controller in a first control apparatus causes a second control apparatus to reboot, when it is detected that a second control apparatus has stopped access operations. The first reboot controller also places a boot event record in a non-volatile storage device of the second control apparatus to indicate that the rebooting of the second control apparatus has been caused by the first control apparatus. After that, a second reboot controller in the second control apparatus causes at least the first control apparatus to reboot while keeping intact the cache data stored in a cache memory of the first control apparatus, when the access controller of the first control apparatus is stopped while the second control apparatus is rebooted, and when a boot event record is found in the non-volatile storage device of the second control apparatus.
    Type: Application
    Filed: August 16, 2011
    Publication date: March 1, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Kazuo Nakashima, Minoru Muramatsu, Hidefumi Kobayashi
  • Patent number: 8078908
    Abstract: An apparatus includes a cache memory for storing user data and control information of the apparatus, a nonvolatile memory and a processor for executing a process including when the power failure occurs, saving the user data and the control information stored in the cache memory into the nonvolatile memory, when the power failure recovers, restoring the data stored in the nonvolatile memory into the cache memory, and erasing the data stored in the nonvolatile memory after restoring the data into the cache memory and when another power failure occurs during erasing the data stored in the nonvolatile memory, erasing the control information stored in the nonvolatile memory if the control information is remained in the nonvolatile memory and saving, into the nonvolatile memory, the updated control information stored in the cache memory and the user data which has been erased from the nonvolatile memory.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Limited
    Inventors: Mihoko Tojo, Hidefumi Kobayashi, Yusuke Oota, Satoshi Hayashi, Keiichi Umezawa