Abstract: In the semiconductor integrated circuit device provided with a plurality of second well regions of the same conductivity type, formed by dividing a first well region provided in the semiconductor substrate by an isolation trench, the isolation trench is substantially linear on the semiconductor substrate surface and the ends reach out of the first well region, however there is no intersection part, namely a corner part T part or cross part in the isolation trench. Therefore, no cavity occurs in the filler in the trench and stress is not concentrated on the intersection part. In addition, defects due to junction leak or mechanical damage do not occur, that is, there is no characteristic deterioration occuring. By providing the second well with memory cell, a semiconductor memory device whose characteristic defect rate and reliability defect rate are remarkably low can be formed.

Abstract: A writing high voltage of one polarity or an erasing high voltage of another polarity is selectively fed, in accordance with a writing or erasing operation mode, via a switch MOSFET to the word line of a non-volatile memory element designated by an address signal. The potential of a well region, where the switch MOSFET is existent, is changed in conformity with the switching action of the relevant switch MOSFET so as to control the switch MOSFET. Due to this arrangement, the potential of the well region with the non-volatile memory elements existing thereon can be retained at a fixed value, so that the high voltage generator is required merely to drive the selected word line of the memory array (and not the well in which the memory elements are formed). Consequently, the requisite current supply capability of the high voltage generator can be diminished.