Patents by Inventor Hidefumi Nishi
Hidefumi Nishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230262884Abstract: A sensor device in which flexibility is ensured over the entirety of the device and that can be manufactured at low costs is provided. The sensor device having flexibility includes a flexible substrate, a temperature/humidity sensor connected to the flexible substrate, and an exterior body formed of a soft material. The temperature/humidity sensor has a waterproof moisture-permeable material that covers a detection surface. The exterior body has an opening that exposes the waterproof moisture-permeable material. The flexible substrate is bonded at at least a peripheral part thereof to the exterior body.Type: ApplicationFiled: June 10, 2021Publication date: August 17, 2023Applicant: DIC CorporationInventors: Shunji Baba, Hidefumi Nishi
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Publication number: 20210262863Abstract: A sensor device to be installed on an installation surface includes: a substrate including a substrate body that is disposed along the installation surface and an extension portion that extends from the substrate body in a direction away from the installation surface; and a temperature sensor that is mounted on the extension portion and that detects an ambient temperature around the sensor device.Type: ApplicationFiled: August 20, 2019Publication date: August 26, 2021Applicant: DIC CorporationInventors: Hidefumi Nishi, Shinichi Tajima, Shunji Baba
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Publication number: 20210041273Abstract: A wireless sensor device (1) includes, on a flexible circuit board (20), at least one sensor selected from the group consisting of a temperature sensor (421), a humidity sensor, an illuminance sensor, and other sensors that sense various environmental conditions; a controller (41) that processes an output value received from the sensor (421); an antenna (43) that wirelessly transmits a signal received from the controller (41); and a primary battery (40). A first adhesive layer (10), the flexible circuit board (20), and a flexible sheet (50) are stacked together.Type: ApplicationFiled: November 27, 2018Publication date: February 11, 2021Applicant: DIC CorporationInventor: Hidefumi Nishi
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Patent number: 8780124Abstract: A graphic processing apparatus includes a chunk assignment unit which assigns a block in which a maximum N number of polygons are located, out of a plurality of polygons drawn in a frame buffer which is divided into a plurality of blocks, to a maximum M number of chunk buffers; a chunk generation unit which generates pixel data of a polygon located in a block assigned to the chunk buffer, out of the N number of polygons, and writes the pixel data to the chunk buffer; and a chunk writing unit which writes the pixel data written in the chunk buffer to the frame buffer, wherein a processing phase, including processing by the chunk assignment unit, processing by the chunk generation unit, and processing by the chunk writing unit, is repeatedly executed for the plurality of polygons.Type: GrantFiled: June 28, 2011Date of Patent: July 15, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Hidefumi Nishi
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Publication number: 20120062578Abstract: A graphic processing apparatus includes a chunk assignment unit which assigns a block in which a maximum N number of polygons are located, out of a plurality of polygons drawn in a frame buffer which is divided into a plurality of blocks, to a maximum M number of chunk buffers; a chunk generation unit which generates pixel data of a polygon located in a block assigned to the chunk buffer, out of the N number of polygons, and writes the pixel data to the chunk buffer; and a chunk writing unit which writes the pixel data written in the chunk buffer to the frame buffer, wherein a processing phase, including processing by the chunk assignment unit, processing by the chunk generation unit, and processing by the chunk writing unit, is repeatedly executed for the plurality of polygons.Type: ApplicationFiled: June 28, 2011Publication date: March 15, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Hidefumi NISHI
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Publication number: 20100079470Abstract: A semiconductor device includes a data acquisition unit which acquires first graphic data including a first drawing position in a drawing region, and acquires second graphic data including a second drawing position different from the first drawing position in the drawing region located later than the first graphic data, a detector which detects positions in a first direction in the drawing region of the first drawing position and the second drawing position, and a controller which causes drawing information at the first drawing position and drawing information at the second drawing position to be continuously stored in a memory when the positions of the first drawing position and the second drawing position in the first direction are similar.Type: ApplicationFiled: August 21, 2009Publication date: April 1, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Hidefumi NISHI
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Patent number: 7554554Abstract: A rendering apparatus includes a low-speed frame buffer, and a first temporary memory and a second temporary memory with high-speed and small capacities. A first/second temporary memory rendering unit blends an image data already stored in the first/second temporary memory and another image data to be blended into the first/second temporary memory, and stores a result of the processing in the first/second temporary memory. A frame buffer rendering unit blends the blended images stored in the first/second temporary memory and a background image stored in the frame buffer.Type: GrantFiled: March 29, 2005Date of Patent: June 30, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Hidefumi Nishi
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Patent number: 7417639Abstract: There are provided a drawing device and an information processing apparatus which are capable of reading out texture data from a memory at a high speed. A storage circuit stores respective information items of each of texture pixels constituting the texture data and at least one texture pixel in a vicinity of the each of the texture pixels, in a continuously-accessible region thereof. An address calculation circuit calculates, based on texture coordinates corresponding to each pixel of the polygons, an address where a corresponding set of the information items are stored. A readout circuit reads out the corresponding set of the information items from the address calculated by the address calculation circuit. A synthesis circuit synthesizes the corresponding set of the information items read out by the readout circuit. A drawing circuit draws, based on texture pixel information synthesized by the synthesis circuit, a corresponding pixel of the polygons.Type: GrantFiled: April 3, 2002Date of Patent: August 26, 2008Assignee: Fujitsu LimitedInventor: Hidefumi Nishi
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Patent number: 7187381Abstract: An apparatus includes a memory which stores therein data of a dotted-line pattern, a unit which identifies successive pixels on a straight line to be drawn with respect to each line of a plurality of straight lines that are drawn side by side, a pattern reference unit which refers to the data of a dotted-line pattern while changing a reference address for accessing the memory in accordance with a slope of a dotted line to be drawn, and a drawing unit which draws the successive pixels in response to the data of a dotted-line pattern referred to by the pattern reference unit.Type: GrantFiled: March 15, 2002Date of Patent: March 6, 2007Assignee: Fujitsu LimitedInventor: Hidefumi Nishi
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Publication number: 20060164419Abstract: A figure dividing unit sequentially generates, on the basis of sequentially input figure data, plural processing unit data respectively representing portions corresponding to plural partial areas constituting an image drawing area of a figure represented by the figure data. Drawing processing units each correspond to at least one of the plural partial areas, and perform, using the processing unit data, drawing processing on the corresponding partial areas independently of one another. A processing assignment unit sequentially determines which one of the drawing processing units should process the processing unit data, on the basis of drawing position information contained in the processing unit data that are sequentially generated by the figure dividing unit.Type: ApplicationFiled: June 10, 2005Publication date: July 27, 2006Inventor: Hidefumi Nishi
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Patent number: 7061499Abstract: An image drawing apparatus includes a first data reading unit which stores a source image data into a first image data buffer. A second data reading unit reads a destination image data from a destination area of a memory device and stores the destination image data into a second image data buffer. A third data reading unit reads a transmission coefficient data from the memory device and stores the transmission coefficient data into a transmission coefficient data buffer. A transmission drawing processing control unit executes a transmission drawing processing for the source image data and the destination image data by using the transmission coefficient data to generate a processed image data. The transmission coefficient data has a block size that is the same as a block size of the source image data, and contains transmission coefficients that are varied with respect to every pixel of the source image data.Type: GrantFiled: October 2, 2002Date of Patent: June 13, 2006Assignee: Fujitsu LimitedInventors: Atsushi Yamada, Hidefumi Nishi
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Patent number: 6954210Abstract: An address converting unit receives pixel coordinates of a display screen in sequence and converts the received pixel coordinates to addresses and offsets. The addresses and offsets obtained from the conversions are stored in buffers in sequence respectively. A buffer controlling unit detects that one of the buffers is full. In response to the detection by the buffer controlling unit, a pixel processing unit modifies pixel data corresponding to the plural addresses read from the memory device according to pixel information. The pixel data stored in the memory device are rewritten according to the pieces of pixel information inputted in correspondence with the pixel coordinates. Therefore, the pieces of pixel data corresponding to the plural addresses are rewritten at a time.Type: GrantFiled: July 9, 2004Date of Patent: October 11, 2005Assignee: Fujitsu LimitedInventor: Hidefumi Nishi
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Publication number: 20050184996Abstract: An address converting unit receives pixel coordinates of a display screen in sequence and converts the received pixel coordinates to addresses and offsets. The addresses and offsets obtained from the conversions are stored in buffers in sequence respectively. A buffer controlling unit detects that one of the buffers is full. In response to the detection by the buffer controlling unit, a pixel processing unit modifies pixel data corresponding to the plural addresses read from the memory device according to pixel information. The pixel data stored in the memory device are rewritten according to the pieces of pixel information inputted in correspondence with the pixel coordinates. Therefore, the pieces of pixel data corresponding to the plural addresses are rewritten at a time.Type: ApplicationFiled: July 9, 2004Publication date: August 25, 2005Inventor: Hidefumi Nishi
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Publication number: 20050168473Abstract: A rendering apparatus includes a low-speed frame buffer, and a first temporary memory and a second temporary memory with high-speed and small capacities. A first/second temporary memory rendering unit blends an image data already stored in the first/second temporary memory and another image data to be blended into the first/second temporary memory, and stores a result of the processing in the first/second temporary memory. A frame buffer rendering unit blends the blended images stored in the first/second temporary memory and a background image stored in the frame buffer.Type: ApplicationFiled: March 29, 2005Publication date: August 4, 2005Inventor: Hidefumi Nishi
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Patent number: 6882444Abstract: In the image drawing apparatus, a drawing position last time is stored in advance in a drawing position memory section, and a linear complementing processing section specifies pixels to be complemented from the last drawing position stored in the drawing position memory section and a drawing this time, and calculates semi-transparent rates of the pixels specified. A semi-transparency processing section then calculates pixel values of the pixels to be complemented by using the calculated semi-transparent rates. Therefore, anti-aliasing processing can be carried out at a high speed.Type: GrantFiled: October 20, 1999Date of Patent: April 19, 2005Assignee: Fujitsu LimitedInventor: Hidefumi Nishi
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Patent number: 6591414Abstract: A binary program conversion apparatus capable of converting an original binary program into a new binary program which runs at higher speed in a target computer having a cache memory. The binary program conversion apparatus comprises an executing part, a generating part and a producing part. The executing part executes the original binary program. The generating part generates executed blocks information indicating first instruction blocks which are executed by the executing part. The producing part produces, based on the executed blocks information generated by the generating part, the new binary program which contains second instruction blocks corresponding to the plural of the first instruction blocks and which causes, when being executed in the computer, the computer to store second instruction blocks corresponding to the first instruction blocks executed by the executing part at different locations of the cache memory.Type: GrantFiled: October 3, 1997Date of Patent: July 8, 2003Assignee: Fujitsu LimitedInventors: Yoshinobu Hibi, Hidefumi Nishi, Toshiki Izuchi, Masaharu Kitaoka
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Publication number: 20030095128Abstract: An image drawing apparatus includes a first data reading unit which stores a source image data into a first image data buffer. A second data reading unit reads a destination image data from a destination area of a memory device and stores the destination image data into a second image data buffer. A third data reading unit reads a transmission coefficient data from the memory device and stores the transmission coefficient data into a transmission coefficient data buffer. A transmission drawing processing control unit executes a transmission drawing processing for the source image data and the destination image data by using the transmission coefficient data to generate a processed image data. The transmission coefficient data has a block size that is the same as a block size of the source image data, and contains transmission coefficients that are varied with respect to every pixel of the source image data.Type: ApplicationFiled: October 2, 2002Publication date: May 22, 2003Applicant: FUJITSU LIMITEDInventors: Atsushi Yamada, Hidefumi Nishi
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Patent number: D766254Type: GrantFiled: October 28, 2013Date of Patent: September 13, 2016Assignee: OLYMPUS CORPORATIONInventors: Maki Kawakami, Hidefumi Nishi
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Patent number: D868082Type: GrantFiled: May 1, 2017Date of Patent: November 26, 2019Assignee: OLYMPUS CORPORATIONInventors: Hidefumi Nishi, Kota Sugaya
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Patent number: D887429Type: GrantFiled: May 1, 2017Date of Patent: June 16, 2020Assignee: OLYMPUS CORPORATIONInventors: Hidefumi Nishi, Kota Sugaya