Patents by Inventor Hidefumi Saeki
Hidefumi Saeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11688641Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.Type: GrantFiled: May 22, 2020Date of Patent: June 27, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidefumi Saeki, Hidehiko Karasaki, Shogo Okita, Atsushi Harikai, Akihiro Itou
-
Patent number: 11551974Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.Type: GrantFiled: September 10, 2021Date of Patent: January 10, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidefumi Saeki, Atsushi Harikai, Shogo Okita
-
Publication number: 20220406660Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer and having a plurality of element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and an individualization step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step including a step of irradiating a first laser beam, to form a first groove exposing the semiconductor layer in the dicing region, and a step of irradiating a second laser beam, with a beam center positioned outside a side wall of the first groove, to widen the first groove into the aperture.Type: ApplicationFiled: June 10, 2022Publication date: December 22, 2022Inventors: Shogo OKITA, Hidehiko KARASAKI, Hidefumi SAEKI, Atsushi HARIKAI
-
Publication number: 20220402072Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer, the substrate having element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and a step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step includes a step of irradiating a first laser beam having a first pulse width, to remove the wiring layer in an edge portion of the dicing region, and a step of irradiating a second laser beam having a second pulse width which is longer than the first pulse width, to remove the wiring layer inside from the edge portion.Type: ApplicationFiled: June 10, 2022Publication date: December 22, 2022Inventors: Hidefumi SAEKI, Hidehiko KARASAKI, Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU
-
Element chip cleaning method, element chip cleaning apparatus, and element chip manufacturing method
Patent number: 11219929Abstract: An element chip cleaning method including: an element chip preparation step of preparing at least one element chip having a first surface and a second surface opposite the first surface, the first surface covered with a resin film; a first cleaning step of bringing a first cleaning liquid into contact with the resin film, the first cleaning liquid including a solvent that dissolves at least part of a resin component contained in the resin film; and a second cleaning step of spraying a second cleaning liquid against the resin film from the first surface side of the element chip, after the first cleaning step.Type: GrantFiled: June 9, 2020Date of Patent: January 11, 2022Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Akihiro Itou, Atsushi Harikai, Toshiyuki Takasaki, Hidefumi Saeki, Shogo Okita -
Publication number: 20210407855Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.Type: ApplicationFiled: September 10, 2021Publication date: December 30, 2021Inventors: Hidefumi SAEKI, Atsushi HARIKAI, Shogo OKITA
-
Patent number: 11145548Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.Type: GrantFiled: March 25, 2019Date of Patent: October 12, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidefumi Saeki, Atsushi Harikai, Shogo Okita
-
Patent number: 10964597Abstract: An element chip manufacturing method including: a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet; a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier; a preprocessing step of preprocessing the substrate, after the placing step; a removing step of removing the second conveying carrier, after the preprocessing step; and a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.Type: GrantFiled: September 11, 2019Date of Patent: March 30, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara, Hidefumi Saeki, Akihiro Itou
-
Patent number: 10896849Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. A method for manufacturing an element chip includes: a step of spray coating, to the first surface of the substrate, a mixture containing a water-soluble resin and an organic solvent having a higher vapor pressure than water, and drying the coated mixture at a temperature of 50° C. or less, to form a protective film; a laser grooving step of removing portions of the protective film covering the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate; and a step of removing the portions of the protective film covering the element regions. The mixture has a solid component ratio of 200 g/L or more, and droplets of the sprayed mixture have an average particle size of 12 ?m or less.Type: GrantFiled: May 30, 2019Date of Patent: January 19, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidehiko Karasaki, Shogo Okita, Noriyuki Matsubara, Hidefumi Saeki
-
Patent number: 10892190Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including dicing regions and element regions, attaching a holding sheet held on a frame with a die attach film in between, forming a protective film covering the substrate, forming a plurality of grooves in the protective film along the dicing regions, plasma-etching the substrate to expose the die attach film and then die attach film along the dicing regions, and picking up each of the element chips along with the separated die attach film away from the holding sheet, wherein the die attach film has an area greater than that of the substrate, and wherein the protective film includes a first covering portion covering the substrate and a second covering portion covering at least a portion of the die attach film that extends beyond an outer edge of the substrate.Type: GrantFiled: January 14, 2019Date of Patent: January 12, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shogo Okita, Atsushi Harikai, Noriyuki Matsubara, Hidefumi Saeki, Akihiro Itou
-
ELEMENT CHIP CLEANING METHOD, ELEMENT CHIP CLEANING APPARATUS, AND ELEMENT CHIP MANUFACTURING METHOD
Publication number: 20200406308Abstract: An element chip cleaning method including: an element chip preparation step of preparing at least one element chip having a first surface and a second surface opposite the first surface, the first surface covered with a resin film; a first cleaning step of bringing a first cleaning liquid into contact with the resin film, the first cleaning liquid including a solvent that dissolves at least part of a resin component contained in the resin film; and a second cleaning step of spraying a second cleaning liquid against the resin film from the first surface side of the element chip, after the first cleaning step.Type: ApplicationFiled: June 9, 2020Publication date: December 31, 2020Inventors: Akihiro ITOU, Atsushi HARIKAI, Toshiyuki TAKASAKI, Hidefumi SAEKI, Shogo OKITA -
Publication number: 20200381304Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.Type: ApplicationFiled: May 22, 2020Publication date: December 3, 2020Inventors: Hidefumi SAEKI, Hidehiko KARASAKI, Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU
-
Patent number: 10843294Abstract: Provided is a laser processing apparatus comprises a stage holding a substrate, the stage being movable in a first direction, a laser beam source radiating a laser beam onto the substrate, a dust-suction duct having a first optical path extending in a second direction perpendicular to the first direction, the laser beam travelling along the first optical path thereof, and an air aspirator aspirating an air toward a direction opposite to the first direction, wherein the dust-suction duct includes a pair of air-guiding plates opposed to each other along a third direction perpendicular to the first and second directions, and wherein the pair of the air-guiding plates are configured to have a gap therebetween such that it is narrowest in an optical path region and gets wider as it is far away from the optical path region in upstream and downstream regions thereof.Type: GrantFiled: April 25, 2018Date of Patent: November 24, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidehiko Karasaki, Hidefumi Saeki
-
Patent number: 10796960Abstract: A manufacturing process of an element chip, comprising a substrate preparing step for preparing a substrate having first and second sides opposed to each other, and including a plurality of dicing regions and element regions defined by the dicing regions, the first side being covered by a protective film, a first laser-grooving step for forming a plurality of grooves by irradiating a laser beam to the first side along the dicing regions, and a plasma-dicing step for plasma-etching the substrate along the grooves in depth through a plasma exposure, thereby to dice the substrate into a plurality of element chips, wherein the second side of the substrate and an annular frame are held on a holding sheet in the substrate preparing step, and wherein the laser beam is irradiated only in a region inside an outer edge of the substrate in the first laser-grooving step.Type: GrantFiled: December 13, 2018Date of Patent: October 6, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidefumi Saeki, Atsushi Harikai
-
Patent number: 10607846Abstract: Method of manufacturing an element chip which can suppress residual debris in plasma dicing. A back surface of a semiconductor wafer is held on a dicing tape. Then, a surface of the wafer is coated with a mask that includes a water-insoluble lower mask and a water-soluble upper mask. Subsequently, an opening is formed in the mask by irradiating the mask with laser light to expose a dividing region. Then, the semiconductor wafer is caused to come into contact with water to remove the upper mask covering each of the element regions while leaving the lower layer. After that, the wafer is exposed to plasma to perform etching on the dividing region exposed from the opening until the etching reaches the back surface, thereby dicing the semiconductor wafer into a plurality of element chips. Thereafter, the lower layer mask left on the front surface of the semiconductor chips is removed.Type: GrantFiled: August 14, 2018Date of Patent: March 31, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidehiko Karasaki, Noriyuki Matsubara, Atsushi Harikai, Hidefumi Saeki
-
Publication number: 20200098636Abstract: An element chip manufacturing method including: a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet; a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier; a preprocessing step of preprocessing the substrate, after the placing step; a removing step of removing the second conveying carrier, after the preprocessing step; and a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.Type: ApplicationFiled: September 11, 2019Publication date: March 26, 2020Inventors: Atsushi HARIKAI, Shogo OKITA, Noriyuki MATSUBARA, Hidefumi SAEKI, Akihiro ITOU
-
Publication number: 20190371669Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. A method for manufacturing an element chip includes: a step of spray coating, to the first surface of the substrate, a mixture containing a water-soluble resin and an organic solvent having a higher vapor pressure than water, and drying the coated mixture at a temperature of 50° C. or less, to form a protective film; a laser grooving step of removing portions of the protective film covering the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate; and a step of removing the portions of the protective film covering the element regions. The mixture has a solid component ratio of 200 g/L or more, and droplets of the sprayed mixture have an average particle size of 12 ?m or less.Type: ApplicationFiled: May 30, 2019Publication date: December 5, 2019Inventors: Hidehiko KARASAKI, Shogo OKITA, Noriyuki MATSUBARA, Hidefumi SAEKI
-
Publication number: 20190304838Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.Type: ApplicationFiled: March 25, 2019Publication date: October 3, 2019Inventors: Hidefumi SAEKI, Atsushi HARIKAI, Shogo OKITA
-
Patent number: 10410924Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step for preparing a substrate including a semiconductor layer having first and second sides and a wiring layer on the first side thereof, the substrate having a plurality of dicing regions and element regions defined by the dicing regions, a scribing step for radiating a laser beam towards the first side of the wiring layer onto the dicing regions to form apertures exposing the semiconductor layer along the dicing regions, and a dicing step for dicing the substrate along the apertures into a plurality of the element chips, wherein the laser beam has a beam profile having a M-shaped distribution whose peripheral intensity is greater than a central intensity in a width direction of the laser beam along the dicing regions.Type: GrantFiled: January 3, 2018Date of Patent: September 10, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidehiko Karasaki, Hidefumi Saeki, Atsushi Harikai
-
Publication number: 20190221479Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including dicing regions and element regions, attaching a holding sheet held on a frame with a die attach film in between, forming a protective film covering the substrate, forming a plurality of grooves in the protective film along the dicing regions, plasma-etching the substrate to expose the die attach film and then die attach film along the dicing regions, and picking up each of the element chips along with the separated die attach film away from the holding sheet, wherein the die attach film has an area greater than that of the substrate, and wherein the protective film includes a first covering portion covering the substrate and a second covering portion covering at least a portion of the die attach film that extends beyond an outer edge of the substrate.Type: ApplicationFiled: January 14, 2019Publication date: July 18, 2019Inventors: Shogo OKITA, Atsushi HARIKAI, Noriyuki MATSUBARA, Hidefumi SAEKI, Akihiro ITOU