Patents by Inventor Hidefumi Yabara
Hidefumi Yabara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8223045Abstract: A D/A converter includes a D/A converter base part having a first D/A converter unit performing D/A conversion of high order bits and a second D/A converter unit performing D/A conversion of low order bits and including an auxiliary bit assigned an identical weight to a least significant bit, a correction D/A converter part, an error detection processing section generating a digital code supplied to a correction D/A converter unit in the correction D/A converter part, and a control section. The control section compares one bit current source with another bit current source in a lower order than the one bit current source, and corrects a value of the one bit current source by causing to supply the digital code to the correction D/A converter unit when the value of the one bit current source changes.Type: GrantFiled: May 18, 2010Date of Patent: July 17, 2012Assignee: Advantest Corp.Inventor: Hidefumi Yabara
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Publication number: 20100314560Abstract: A D/A converter includes a D/A converter base part having a first D/A converter unit performing D/A conversion of high order bits and a second D/A converter unit performing D/A conversion of low order bits and including an auxiliary bit assigned an identical weight to a least significant bit, a correction D/A converter part, an error detection processing section generating a digital code to be set to a correction D/A converter unit in the correction D/A converter part, and a control section. The control section compares one bit current source with another bit current source in a lower order than the one bit current source, and corrects a value of the one bit current source by causing the error detection processing section to generate the digital code to be set to the correction D/A converter unit when judging that the value of the one bit current source changes.Type: ApplicationFiled: May 18, 2010Publication date: December 16, 2010Inventor: Hidefumi Yabara
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Publication number: 20080049204Abstract: A multi-column type electron beam exposure apparatus includes: plural column cells disposed over a wafer, each including an electron gun, deflector for deflecting an electron beam emitted by the electron gun, and exposure data receiving unit for receiving exposure data; and correction computing unit for calculating the exposure data for use in the column cells. The correction computing unit includes exposure data controlling unit and exposure data transmitting unit for each of the column cells. The exposure data transmitting unit encodes the exposure data corrected by the exposure data controlling unit to convert the data into serial data, converts the serial data into a light signal, and transmits the light signal. The exposure data receiving unit converts the light signal into an electric signal, and decodes the encoded exposure data to convert the data into parallel data.Type: ApplicationFiled: August 30, 2007Publication date: February 28, 2008Inventors: Hidefumi Yabara, Kenichi Miyazawa, Tomohiro Sakazaki, Kazuaki Tanaka
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Patent number: 6399954Abstract: Disclosed is a charged-particle beam lithography apparatus capable of readily detecting an abnormality in controlling the on-off operation of a charged-particle beam. The charged-particle beam lithography apparatus consists of a charged-particle beam generator, a charged-particle beam reshaping unit, a charged-particle beam converging unit, a charged-particle beam deflecting unit, a blanking unit, a digital converting circuit, and a comparing circuit. The blanking unit produces a blanking signal used to control the on-off operation of a charged-particle beam according to exposure pattern data, and thus controls the on-off operation of the charged-particle beam. The digital converting circuit produces a blanking data signal that is a digital signal indicating a variation of the blanking signal. The comparing circuit compares the blanking data signal with the exposure pattern data. It is detected whether the on-off operation of the charged-particle beam is controlled according to the exposure pattern data.Type: GrantFiled: February 2, 1999Date of Patent: June 4, 2002Assignee: Advantest CorporationInventors: Isamu Seto, Atsushi Saito, Hidefumi Yabara
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Publication number: 20010013581Abstract: A method of exposing a wafer to a charged-particle beam by directing to the wafer the charged-particle beam deflected by a deflector includes the steps of arranging a plurality of first marks at different heights, focusing the charged-particle beam on each of the first marks by using a focus coil provided above the deflector, obtaining a focus distance for each of the first marks, obtaining deflection-efficiency-correction coefficients for each of the first marks, and using linear functions of the focus distance for approximating the deflection-efficiency-correction coefficients to obtain the deflection-efficiency-correction coefficients for an arbitrary value of the focus distance. A device for carrying out the method is also set forth.Type: ApplicationFiled: April 6, 2001Publication date: August 16, 2001Inventors: Akio Takemoto, Yoshihisa Ooaeh, Tomohiko Abe, Hiroshi Yasuda, Takamasa Satoh, Hideki Nasuno, Hidefumi Yabara, Kenichi Kawakami, Kiichi Sakamoto, Tomohiro Sakazaki, Isamu Seto, Masami Takigawa, Tatsuro Ohkawa
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Patent number: 6242751Abstract: A method of exposing a wafer to a charged-particle beam by directing to the wafer the charged-particle beam deflected by a deflector includes the steps of arranging a plurality of first marks at different heights, focusing the charged-particle beam on each of the first marks by using a focus coil provided above the deflector, obtaining a focus distance for each of the first marks, obtaining deflection-efficiency-correction coefficients for each of the first marks, and using linear functions of the focus distance for approximating the deflection-efficiency-correction coefficients to obtain the deflection-efficiency-correction coefficients for an arbitrary value of the focus distance. A device for carrying out the method is also set forth.Type: GrantFiled: July 15, 1999Date of Patent: June 5, 2001Assignee: Fujitsu LimitedInventors: Akio Takemoto, Yoshihisa Ooaeh, Tomohiko Abe, Hiroshi Yasuda, Takamasa Satoh, Hideki Nasuno, Hidefumi Yabara, Kenichi Kawakami, Kiichi Sakamoto, Tomohiro Sakazaki, Isamu Seto, Masami Takigawa, Tatsuro Ohkawa
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Patent number: 6072185Abstract: A device exposing a wafer to charged-particle beams in an exposure process generates a plurality of micro beams and controls deflection of each of the micro beams, relative to whether or not the micro beams reach the wafer, in accordance with control data. A data processing unit inserts data-position-adjustment data into the control data for each exposure. A first data-storage unit stores the control data, inserted with the data-position-adjustment data, and outputs the control data at a time of the exposure process. Storage positions of the control data in the first data-storage unit are adjusted by the data-position-adjustment data so that the control data can be continuously read from the first data-storage unit for maintaining a continuous exposure process.Type: GrantFiled: November 18, 1997Date of Patent: June 6, 2000Assignee: Fujitsu LimitedInventors: Soichiro Arai, Kenichi Miyazawa, Hidefumi Yabara, Hiroshi Yasuda
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Patent number: 5969365Abstract: A method of exposing a wafer to a charged-particle beam by directing to the wafer the charged-particle beam deflected by a deflector includes the steps of arranging a plurality of first marks at different heights, focusing the charged-particle beam on each of the first marks by using a focus coil provided above the deflector, obtaining a focus distance for each of the first marks, obtaining deflection-efficiency-correction coefficients for each of the first marks, and using linear functions of the focus distance for approximating the deflection-efficiency-correction coefficients to obtain the deflection-efficiency-correction coefficients for an arbitrary value of the focus distance. A device for carrying out the method is also set forth.Type: GrantFiled: August 26, 1997Date of Patent: October 19, 1999Assignee: Fujitsu LimitedInventors: Akio Takemoto, Yoshihisa Ooaeh, Tomohiko Abe, Hiroshi Yasuda, Takamasa Satoh, Hideki Nasuno, Hidefumi Yabara, Kenichi Kawakami, Kiichi Sakamoto, Tomohiro Sakazaki, Isamu Seto, Masami Takigawa, Tatsuro Ohkawa
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Patent number: 5965895Abstract: A method for providing charged particle beam exposure onto an object having a plurality of chip areas with a plurality of aligning marks formed in correspondence to each of said chip areas. A charged particle beam is irradiated upon an object mounted on a mobile step based upon positions of the aligning marks. Actual positions of the alignment marks are detected and compared to the design positions of the alignment marks to determine approximate relationships which are used to calculate an actual position to perform exposure.Type: GrantFiled: November 4, 1997Date of Patent: October 12, 1999Assignee: Fujitsu LimitedInventors: Takamasa Satoh, Hiroshi Yasuda, Junichi Kai, Yoshihisa Oae, Hisayasu Nishino, Kiichi Sakamoto, Hidefumi Yabara, Isamu Seto, Masami Takigawa, Akio Yamada, Soichiro Arai, Tomohiko Abe, Takashi Kiuchi, Kenichi Miyazawa
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Patent number: 5910658Abstract: Adjusting variable delay circuit 311, receiving signal S1, is connected to the input of drive circuit 312. A time point t1, when the output potential of drive circuit 312 traverses reference potential VA between the potential Va of traveling wave V1F of the output potential and 0 V, is detected by comparator 52 for detecting the front edge of V1F, detecting variable delay circuit 50 for delaying signal S1 and D flip-flop 51 for holding the output of comparator 52 at the timing of front edge of the signal outputted from delay circuit 50. A time point t2, when the output potential of drive circuit 312 traverses reference potential VB between the superimposed potential of traveling wave V1F and reflected wave V1B and VA, is detected by comparator 62 for detecting the front edge of V1B, detecting variable delay circuit 60 for delaying signal S1 and D flip-flop 61 for holding the output of comparator 62 at the timing of front edge of the signal outputted from delay circuit 60.Type: GrantFiled: February 20, 1998Date of Patent: June 8, 1999Assignees: Fujitsu Limited, Advantest CorporationInventors: Soichiro Arai, Kenichi Miyazawa, Hidefumi Yabara, Hiroshi Yasuda, Takayuki Nakatani
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Patent number: 5808313Abstract: The object of the present invention is to ensure a correct exposure even when a single exposure apparatus is used to expose a predetermined pattern, and an exposure apparatus therefor.Type: GrantFiled: July 15, 1997Date of Patent: September 15, 1998Assignee: Fujitsu LimitedInventors: Akio Yamada, Hiroshi Yasuda, Hidefumi Yabara, Atsushi Saito
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Patent number: 5757015Abstract: A method of exposing a wafer to a charged-particle beam by directing to the wafer the charged-particle beam deflected by a deflector includes the steps of arranging a plurality of first marks at different heights, focusing the charged-particle beam on each of the first marks by using a focus coil provided above the deflector, obtaining a focus distance for each of the first marks, obtaining deflection-efficiency-correction coefficients for each of the first marks, and using linear functions of the focus distance for approximating the deflection-efficiency-correction coefficients to obtain the deflection-efficiency-correction coefficients for an arbitrary value of the focus distance. A device for carrying out the method is also set forth.Type: GrantFiled: April 18, 1996Date of Patent: May 26, 1998Assignee: Fujitsu LimitedInventors: Akio Takemoto, Yoshihisa Ooaeh, Tomohiko Abe, Hiroshi Yasuda, Takamasa Satoh, Hideki Nasuno, Hidefumi Yabara, Kenichi Kawakami, Kiichi Sakamoto, Tomohiro Sakazaki, Isamu Seto, Masami Takigawa, Tatsuro Ohkawa
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Patent number: 5721432Abstract: To improve in the throughput of an exposure system, the setting time during a step change in the output of an amplifier is reduced by switching resistance between the amplifier and deflector, a glitch waveform generated during a step change in the output of a D/A converter at the preceding stage of the amplifier, is anticipated and is canceled out with a correction waveform, after the output of the D/A converter has settled, this output is sample held and the step change is interpolated at a smoothing circuit, the deflection area is increased by positioning a electrostatic deflector offset around the optical axis relative to another electrostatic deflector, the response speed of the main deflection is improved by adding auxiliary deflection coils of one or two turn, and the alignment time is reduced by combining the coordinate conversion in the wafer area and in the chip area.Type: GrantFiled: June 20, 1996Date of Patent: February 24, 1998Assignee: Fujitsu LimitedInventors: Takamasa Satoh, Hiroshi Yasuda, Junichi Kai, Yoshihisa Oae, Hisayasu Nishino, Kiichi Sakamoto, Hidefumi Yabara, Isamu Seto, Masami Takigawa, Akio Yamada, Soichiro Arai, Tomohiko Abe, Takashi Kiuchi, Kenichi Miyazawa
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Patent number: 5719402Abstract: To improve the throughput of an exposure system, the setting time during a step change in the output of an amplifier is reduced by switching resistance between the amplifier and a deflector. A glitch waveform generated during a step change in the output of a D/A converter at the preceding stage of the amplifier is anticipated and is cancelled out with a correction waveform. After the output of the D/A converter has settled, this output is sample-held and the step change is interpolated with a smoothing circuit. The deflection area is increased by positioning an electrostatic deflector offset around the optical axis relative to another electrostatic deflector, and the response speed of the main deflection is improved by adding auxiliary deflection coils of one or two turns. The alignment time is reduced by combining the coordinate conversion in the wafer area and in the chip area.Type: GrantFiled: April 4, 1996Date of Patent: February 17, 1998Assignee: Fujitsu LimitedInventors: Takamasa Satoh, Hiroshi Yasuda, Junichi Kai, Yoshihisa Oae, Hisayasu Nishino, Kiichi Sakamoto, Hidefumi Yabara, Isamu Seto, Masami Takigawa, Akio Yamada, Soichiro Arai, Tomohiko Abe, Takashi Kiuchi, Kenichi Miyazawa
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Patent number: 5546319Abstract: To improve in the throughput of an exposure system, the setting time during a step change in the output of an amplifier is reduced by switching resistance between the amplifier and a deflector, a glitch waveform generated during a step change in the output or a D/A converter at the preceding stage of the amplifier, is anticipated and is canceled out with a correction waveform, after the output of the D/A converter has settled, this output is sample held and the step change is interpolated at a smoothing circuit, the deflection area is increased by positioning a electrostatic deflector offset around the optical axis relative to another electrostatic deflector, the response speed of the main deflection is improved by adding auxiliary deflection coils of one or two turn, and the alignment time is reduced by combining the coordinate conversion in the wafer area and in the chip area.Type: GrantFiled: January 27, 1995Date of Patent: August 13, 1996Assignee: Fujitsu LimitedInventors: Takamasa Satoh, Hiroshi Yasuda, Junichi Kai, Yoshihisa Oae, Hisayasu Nishino, Kiichi Sakamoto, Hidefumi Yabara, Isamu Seto, Masami Takigawa, Akio Yamada, Soichiro Arai, Tomohiko Abe, Takashi Kiuchi, Kenichi Miyazawa
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Patent number: 5134398Abstract: A D/A converter converting a digital signal having n bits (n is an integer) into an analog signal includes constant-current output circuits, provided for the n bits of the digital signal, for selectively generating n constant currents on the basis of the n bits of the digital signals. The n constant currents have mutually different current values with respect to the n bits of the digital signal. The constant-current output circuits have resistance elements respectively provided for the n bits of the digital signal. The resistance elements define the mutually different current values. The D/A converter also includes an output circuit for adding the n constant currents to each other and for outputting the analog signal based on an addition result, and a temperature-dependent voltage generating part for generating a temperature-dependent voltage which changes as a temperature around the D/A converter changes.Type: GrantFiled: March 19, 1991Date of Patent: July 28, 1992Assignee: Fujitsu LimitedInventors: Nobuyuki Yasutake, Hidefumi Yabara