Patents by Inventor Hideharu Fujii

Hideharu Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4484206
    Abstract: A first rectifying contact portion of a semiconductor device such as a Zener diode has a small area in order to attain a hard breakdown characteristic and a low noise characteristic. When a predetermined current which is not greater than the maximum allowable instantaneous value of non-D.C. currents flows through the first rectifying contact portion, a second rectifying contact portion which has a large area starts breakdown due to a voltage drop across a resistance component connected in series with the first rectifying contact portion and a breakdown voltage of the first rectifying contact portion.Owing to the fact that current is dispersed to the first rectifying contact portion and the second rectifying contact portion, a semiconductor device such as a Zener diode exhibiting a high endurance characteristic against surge voltages can be provided.
    Type: Grant
    Filed: February 26, 1982
    Date of Patent: November 20, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Heiji Moroshima, Hajime Terakado, Hideharu Fujii
  • Patent number: 4405932
    Abstract: This invention is directed to a punch-through reference diode comprising a first semiconductor region of a first conductivity type which is formed within a semiconductor body; a second semiconductor region of a second conductivity type which is formed within the semiconductor body, the second semiconductor region adjoining the first semiconductor region and defining a first PN-junction with the first semiconductor region; and a third semiconductor region of the first conductivity type which is formed within the semiconductor body, the third semiconductor region adjoining the second semiconductor region and defining a second PN-junction with the second semiconductor region, whereby the second semiconductor region is located between the first PN-junction and the second PN-junction.
    Type: Grant
    Filed: December 29, 1980
    Date of Patent: September 20, 1983
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Kiyoichi Ishii, Hideharu Fujii, Kenji Kobayashi