Patents by Inventor Hideharu Kashima

Hideharu Kashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7881542
    Abstract: A coding apparatus that can have a plurality of macro blocks processed concurrently. The apparatus includes a plurality of macro block processing sections for coding moving picture data concurrently on a macro block by macro block basis, and a state management section for managing the state of processing of each macro block in a single picture. The state management section being adapted to manage each macro block in a single picture in terms of being in a process completed state.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: February 1, 2011
    Assignee: Sony Corporation
    Inventors: Hideharu Kashima, Daisuke Hiranaka, Yukio Yanagita
  • Patent number: 7881541
    Abstract: A coding apparatus that can have a plurality of macro blocks processed concurrently macro blocks. The apparatus includes a plurality of macro block processing sections for coding moving picture data concurrently on a macro block by macro block basis, each macro block processing section being adapted to select a position or a region out of a plurality of regions produced by dividing a picture by a predetermined number of rows, detect a processable macro block by sequentially retrieving the macro blocks of the selected region according to a predetermined scanning sequence and code the detected processable macro block.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: February 1, 2011
    Assignee: Sony Corporation
    Inventors: Hideharu Kashima, Daisuke Hiranaka, Yukio Yanagita
  • Publication number: 20060093043
    Abstract: A coding apparatus that can have a plurality of macro blocks processed concurrently according to a new standard such as the MPEG-4 Standard or the H. 264/MPEG-4AVC Standard.
    Type: Application
    Filed: October 27, 2005
    Publication date: May 4, 2006
    Inventors: Hideharu Kashima, Daisuke Hiranaka, Yukio Yanagita
  • Publication number: 20060093042
    Abstract: A coding apparatus that can have a plurality of macro blocks processed concurrently according to a new standard such as the MPEG-4 Standard or the H. 264/MPEG-4AVC Standard.
    Type: Application
    Filed: October 27, 2005
    Publication date: May 4, 2006
    Inventors: Hideharu Kashima, Daisuke Hiranaka, Yukio Yanagita