Patents by Inventor Hideharu KOJIMA
Hideharu KOJIMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230116560Abstract: A semiconductor device according to an embodiment includes: a first electrode; and a substrate including a first surface in contact with the first electrode and a second surface provided opposite to the first surface, the first surface including a first groove including a first length and a second length shorter than the first length, the first length in a first direction parallel to the first surface, the second length in a second direction parallel to the first surface, the second direction intersecting with the first direction, wherein the substrate includes a semiconductor layer having first conductive type, a first semiconductor region provided between the semiconductor layer and the second surface, the first semiconductor region having second conductive type, a second semiconductor region provided between the first semiconductor region and the second surface, the second semiconductor region having first conductive type higher than an impurity concentration of the semiconductor layer, and a second electrType: ApplicationFiled: December 14, 2022Publication date: April 13, 2023Inventor: Hideharu Kojima
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Patent number: 11594476Abstract: A semiconductor device includes: a first chip including first and second electrodes provided at a first surface, and a third electrode provided at a second surface positioned at a side opposite to the first surface; a second chip including fourth and fifth electrodes provided at a third surface, and a sixth electrode provided at a fourth surface positioned at a side opposite to the third surface, wherein the second chip is disposed to cause the third surface to face the first surface; a first connector disposed between the first electrode and the fourth electrode and connected to the first and fourth electrodes; and a second connector disposed between the second electrode and the fifth electrode and connected to the second and fifth electrodes.Type: GrantFiled: March 15, 2021Date of Patent: February 28, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Tatsuya Ohguro, Hideharu Kojima
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Patent number: 11569377Abstract: A semiconductor device according to an embodiment includes: a first electrode; and a substrate including a first surface in contact with the first electrode and a second surface provided opposite to the first surface, the first surface including a first groove including a first length and a second length shorter than the first length, the first length in a first direction parallel to the first surface, the second length in a second direction parallel to the first surface, the second direction intersecting with the direction, wherein the substrate includes a semiconductor layer having first conductive type, a first semiconductor region provided between the semiconductor layer and the second surface, the first semiconductor region having second conductive type, a second semiconductor region provided between the first semiconductor region and the second surface, the second semiconductor region having first conductive type higher than an impurity concentration of the semiconductor layer, and a second electrode prType: GrantFiled: February 26, 2021Date of Patent: January 31, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Hideharu Kojima
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Publication number: 20220093787Abstract: A semiconductor device according to an embodiment includes: a first electrode; and a substrate including a first surface in contact with the first electrode and a second surface provided opposite to the first surface, the first surface including a first groove including a first length and a second length shorter than the first length, the first length in a first direction parallel to the first surface, the second length in a second direction parallel to the first surface, the second direction intersecting with the direction, wherein the substrate includes a semiconductor layer having first conductive type, a first semiconductor region provided between the semiconductor layer and the second surface, the first semiconductor region having second conductive type, a second semiconductor region provided between the first semiconductor region and the second surface, the second semiconductor region having first conductive type higher than an impurity concentration of the semiconductor layer, and a second electrode prType: ApplicationFiled: February 26, 2021Publication date: March 24, 2022Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation, Toshiba Electronic Devices & Storage CorporationInventor: Hideharu Kojima
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Publication number: 20220084917Abstract: A semiconductor device includes: a first chip including first and second electrodes provided at a first surface, and a third electrode provided at a second surface positioned at a side opposite to the first surface; a second chip including fourth and fifth electrodes provided at a third surface, and a sixth electrode provided at a fourth surface positioned at a side opposite to the third surface, wherein the second chip is disposed to cause the third surface to face the first surface; a first connector disposed between the first electrode and the fourth electrode and connected to the first and fourth electrodes; and a second connector disposed between the second electrode and the fifth electrode and connected to the second and fifth electrodes.Type: ApplicationFiled: March 15, 2021Publication date: March 17, 2022Inventors: Tatsuya Ohguro, Hideharu Kojima
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Patent number: 10998437Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a semiconductor element provided in the semiconductor substrate, the semiconductor element including a gate insulating film provided in the first plane, a first electrode provided on the first plane, a second electrode provided on the first electrode, the second electrode including a first metal material, the second electrode having a film thickness of (65 [g·?m·cm?3])/(density of the first metal material [g·cm?3]) or more, a first solder portion provided on the second electrode, a third electrode provided on the first solder portion, a fourth electrode provided on the first plane, a fifth electrode provided on the fourth electrode, the fifth electrode including a second metal material, the fifth electrode having a film thickness of (65 [g·?m·cm?3])/(density of the second metal material [g·cm?3]) or more, a second solder portion provided on the fifth electrode, and a sixth electrode prType: GrantFiled: August 5, 2019Date of Patent: May 4, 2021Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Tatsuya Ohguro, Tatsuya Nishiwaki, Hideharu Kojima, Yoshiharu Takada, Kikuo Aida, Kentaro Ichinoseki, Kohei Oasa, Shingo Sato
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Patent number: 10825756Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, and a die pad. The die pad has a first surface. The semiconductor chip is bonded on the first surface using a paste including a metal particle. A concave structure is provided in the first surface. The concave structure is positioned directly under each of a plurality of sides of the semiconductor chip and extends along each of the plurality of sides.Type: GrantFiled: March 4, 2019Date of Patent: November 3, 2020Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Hideharu Kojima, Yoshiharu Takada
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Publication number: 20200152785Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a semiconductor element provided in the semiconductor substrate, the semiconductor element including a gate insulating film provided in the first plane, a first electrode provided on the first plane, a second electrode provided on the first electrode, the second electrode including a first metal material, the second electrode having a film thickness of (65 [g·?m·cm?3])/(density of the first metal material [g·cm?3]) or more, a first solder portion provided on the second electrode, a third electrode provided on the first solder portion, a fourth electrode provided on the first plane, a fifth electrode provided on the fourth electrode, the fifth electrode including a second metal material, the fifth electrode having a film thickness of (65 [g·m·cm?3])/(density of the second metal material [g·cm?3]) or more, a second solder portion provided on the fifth electrode, and a sixth electrode proType: ApplicationFiled: August 5, 2019Publication date: May 14, 2020Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Tatsuya OHGURO, Tatsuya NISHIWAKI, Hideharu KOJIMA, Yoshiharu TAKADA, Kikuo AIDA, Kentaro ICHINOSEKI, Kohei OASA, Shingo SATO
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Publication number: 20200075464Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, and a die pad. The die pad has a first surface. The semiconductor chip is bonded on the first surface using a paste including a metal particle. A concave structure is provided in the first surface. The concave structure is positioned directly under each of a plurality of sides of the semiconductor chip and extends along each of the plurality of sides.Type: ApplicationFiled: March 4, 2019Publication date: March 5, 2020Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELETRONIC DEVICES & STORAGE CORPORATIONInventors: Hideharu KOJIMA, Yoshiharu Takada