Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory in formation from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: The present invention provides a semiconductor memory capable of shortening a refresh cycle time and reducing power consumption at refresh. The semiconductor memory includes an address input circuit for generating each of internal address signals, a redundant judgement circuit for receiving the internal address signal therein and determining whether the corresponding address corresponds to an address for a defective word line of a plurality of normal word lines, and an address counter for generating refresh address signals for sequentially refreshing the plurality of normal word lines and redundant word lines. The redundant judgment circuit is deactivated upon refresh.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the column address signal transition detector.