Patents by Inventor Hideharu YOSHIOKA

Hideharu YOSHIOKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210151850
    Abstract: According to the present invention, there is provided a power divider/combiner in which two transmission lines configured to connect between respective input/output terminals and an isolation resistor are at least partially adjusted to have suitable impedances during an even-mode operation and an odd-mode operation, for each of the even mode operation and the odd mode operation, to thereby ensure satisfactory reflection characteristics at the respective input/output terminals during the odd-mode operation, a satisfactory reflection characteristic at a common terminal during the even-mode operation, and satisfactory reflection characteristics at the respective input/output terminals during the even-mode operation over a wide band.
    Type: Application
    Filed: June 28, 2017
    Publication date: May 20, 2021
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideharu YOSHIOKA, Hiroyuki AOYAMA, Naofumi YONEDA, Tetsuro ASHIDA
  • Patent number: 10971792
    Abstract: Provided is a structure configured to electrically connect multi-layer dielectric waveguides, each including a dielectric waveguide formed of conductor patterns and vias in a laminating direction of the multi-layer dielectric substrate, in which the vias for forming part of a waveguide wall of each of the dielectric waveguides are arranged in a staggered pattern in the multi-layer dielectric substrate side having choke structures formed so as to electrically connect the waveguides to each other.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: April 6, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideharu Yoshioka, Yasuo Morimoto, Naofumi Yoneda, Akimichi Hirota, Tomokazu Hamada, Tsuyoshi Hatate
  • Patent number: 10964631
    Abstract: A semiconductor package includes a package main body. The package main body includes: a lead frame that includes first terminals and a die pad; two or more integrated circuit chips that are disposed on the die pad; one or more electrically conductive members that are disposed on the die pad; wires that connect the first terminals and the integrated circuit chips electrically; and a molded member that seals the lead frame, the integrated circuit chips, the electrically conductive member, and the wires. An upper surface, a bottom surface, and side surfaces of the package main body are formed by the molded member. The electrically conductive member is exposed through the upper surface of the package main body, and the die pad is exposed through the bottom surface of the package main body.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: March 30, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideharu Yoshioka, Akimichi Hirota, Naofumi Yoneda, Hidenori Ishibashi, Shintaro Shinjo, Kiyoshi Ishida, Hideki Morishige
  • Publication number: 20210083353
    Abstract: To obtain a downsized dielectric filter suitable for a laminating structure, a dielectric filter is configured with use of a dielectric waveguide formed of a conductor pattern and vias in a laminating direction within a multilayer dielectric substrate, two strip lines formed in a planar direction of the multilayer dielectric substrate, and two strip line-waveguide converters each configured to perform transmission line conversion between the dielectric waveguide and each strip line. In this manner, it is possible to provide a dielectric filter for which an area to be occupied in the planar direction of the multilayer dielectric substrate is suppressed.
    Type: Application
    Filed: June 7, 2018
    Publication date: March 18, 2021
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideharu YOSHIOKA, Akimichi HIROTA, Takeshi YUASA, Tomokazu HAMADA, Yasuo MORIMOTO
  • Patent number: 10930995
    Abstract: Provided is a power divider/combiner capable of improving reflection characteristics and isolation characteristics. The power divider/combiner is formed by a multilayer board, and a strip conductor is arranged in an inner layer of the multilayer board and a chip resistor is arranged on an outer surface of the multilayer board. The power divider/combiner includes vias, which connect the strip conductor and the chip resistor, and includes stubs mounted between input/output terminals and the vias. With this configuration, it is possible to adjust induction mainly during an odd mode of an even/odd mode operation and to consequently improve reflection characteristics of the input/output terminals and isolation characteristics between the input/output terminals.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: February 23, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideharu Yoshioka, Akimichi Hirota, Naofumi Yoneda, Hidenori Ishibashi
  • Publication number: 20200235456
    Abstract: Provided is a power divider/combiner capable of improving reflection characteristics and isolation characteristics. The power divider/combiner is formed by a multilayer board, and a strip conductor is arranged in an inner layer of the multilayer board and a chip resistor is arranged on an outer surface of the multilayer board. The power divider/combiner includes vias, which connect the strip conductor and the chip resistor, and includes stubs mounted between input/output terminals and the vias. With this configuration, it is possible to adjust induction mainly during an odd mode of an even/odd mode operation and to consequently improve reflection characteristics of the input/output terminals and isolation characteristics between the input/output terminals.
    Type: Application
    Filed: February 2, 2017
    Publication date: July 23, 2020
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideharu YOSHIOKA, Akimichi HIROTA, Naofumi YONEDA, Hidenori ISHIBASHI
  • Publication number: 20200126896
    Abstract: A semiconductor package includes a package main body. The package main body includes: a lead frame that includes first terminals and a die pad; two or more integrated circuit chips that are disposed on the die pad; one or more electrically conductive members that are disposed on the die pad; wires that connect the first terminals and the integrated circuit chips electrically; and a molded member that seals the lead frame, the integrated circuit chips, the electrically conductive member, and the wires. An upper surface, a bottom surface, and side surfaces of the package main body are formed by the molded member. The electrically conductive member is exposed through the upper surface of the package main body, and the die pad is exposed through the bottom surface of the package main body.
    Type: Application
    Filed: February 25, 2016
    Publication date: April 23, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hideharu YOSHIOKA, Akimichi HIROTA, Naofumi YONEDA, Hidenori ISHIBASHI, Shintaro SHINJO, Kiyoshi ISHIDA, Hideki MORISHIGE
  • Publication number: 20200028228
    Abstract: Provided is a structure configured to electrically connect multi-layer dielectric waveguides, each including a dielectric waveguide formed of conductor patterns and vias in a laminating direction of the multi-layer dielectric substrate, in which the vias for forming part of a waveguide wall of each of the dielectric waveguides are arranged in a staggered pattern in the multi-layer dielectric substrate side having choke structures formed so as to electrically connect the waveguides to each other.
    Type: Application
    Filed: April 12, 2017
    Publication date: January 23, 2020
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideharu YOSHIOKA, Yasuo MORIMOTO, Naofumi YONEDA, Akimichi HIROTA, Tomokazu HAMADA, Tsuyoshi HATATE
  • Patent number: 10512153
    Abstract: A printed wiring board includes conductor layers, a core layer having an opening, and a build-up layer. A high frequency device placed within the opening is installed such that a mirror surface is thermally connected to a conductor layer for heat dissipation facing the opening from a lower surface side of the core layer, and terminals on the terminal surface are electrically connected to conductor layers formed on an upper surface side of the core layer.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: December 17, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hidenori Ishibashi, Kiyoshi Ishida, Eigo Kuwata, Yukinobu Tarui, Hideharu Yoshioka, Hiroyuki Aoyama, Masaomi Tsuru
  • Patent number: 10438862
    Abstract: A recess in a metal housing accommodating a high frequency package includes a first space and a second space and has a winners podium shape in cross-sectional view. A thermally conductive material is sandwiched between the metal housing having heat dissipating fins and the high frequency package.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: October 8, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuo Morimoto, Hideharu Yoshioka, Akimichi Hirota, Naofumi Yoneda, Takuma Ishibashi
  • Patent number: 10396039
    Abstract: A lead frame includes: a second terminal that is disposed to surround terminals on a package plane and can be grounded; and a conductive member that covers molded resin and is electrically connected to the second terminal.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: August 27, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Mizutani, Hidenori Ishibashi, Hideharu Yoshioka, Kiyoshi Ishida
  • Publication number: 20190159332
    Abstract: A printed wiring board includes conductor layers, a core layer having an opening, and a build-up layer. A high frequency device placed within the opening is installed such that a mirror surface is thermally connected to a conductor layer for heat dissipation facing the opening from a lower surface side of the core layer, and terminals on the terminal surface are electrically connected to conductor layers formed on an upper surface side of the core layer.
    Type: Application
    Filed: April 27, 2016
    Publication date: May 23, 2019
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hidenori ISHIBASHI, Kiyoshi ISHIDA, Eigo KUWATA, Yukinobu TARUI, Hideharu YOSHIOKA, Hiroyuki AOYAMA, Masaomi TSURU
  • Publication number: 20180308776
    Abstract: A recess in a metal housing accommodating a high frequency package includes a first space and a second space and has a winners podium shape in cross-sectional view. A thermally conductive material is sandwiched between the metal housing having heat dissipating fins and the high frequency package.
    Type: Application
    Filed: December 24, 2015
    Publication date: October 25, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yasuo MORIMOTO, Hideharu YOSHIOKA, Akimichi HIROTA, Naofumi YONEDA, Takuma ISHIBASHI
  • Publication number: 20170330838
    Abstract: A lead frame includes: a second terminal that is disposed to surround terminals on a package plane and can be grounded; and a conductive member that covers molded resin and is electrically connected to the second terminal.
    Type: Application
    Filed: December 9, 2014
    Publication date: November 16, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroyuki MIZUTANI, Hidenori ISHIBASHI, Hideharu YOSHIOKA, Kiyoshi ISHIDA
  • Patent number: 9184485
    Abstract: Disclosed is a directional coupler including a broadside coupled line 1031 provided with a main signal line conductor 1001 and a secondary signal line conductor 1011 arranged in parallel with the main signal line conductor 1001, and an offset broadside coupled line 1032 provided with a main signal line conductor 1002 having an end portion connected to an end portion of the main signal line conductor 1001 and a second secondary signal line conductor 1012 having an end portion connected to an end portion of the secondary signal line conductor 1011, and arranged in parallel with the main signal line conductor 1002, in which a coupled line impedance in the broadside coupled line 1031 is lower than a terminal impedance and a coupled line impedance in the offset broadside coupled line 1032 is higher than the terminal impedance.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: November 10, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hideharu Yoshioka, Akimichi Hirota, Tetsu Owada, Shinsuke Watanabe, Kazuhiro Iyomasa, Kazuya Yamamoto
  • Publication number: 20140292439
    Abstract: Disclosed is a directional coupler including a broadside coupled line 1031 provided with a main signal line conductor 1001 and a secondary signal line conductor 1011 arranged in parallel with the main signal line conductor 1001, and an offset broadside coupled line 1032 provided with a main signal line conductor 1002 having an end portion connected to an end portion of the main signal line conductor 1001 and a second secondary signal line conductor 1012 having an end portion connected to an end portion of the secondary signal line conductor 1011, and arranged in parallel with the main signal line conductor 1002, in which a coupled line impedance in the broadside coupled line 1031 is lower than a terminal impedance and a coupled line impedance in the offset broadside coupled line 1032 is higher than the terminal impedance.
    Type: Application
    Filed: March 25, 2014
    Publication date: October 2, 2014
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideharu YOSHIOKA, Akimichi HIROTA, Tetsu OWADA, Shinsuke WATANABE, Kazuhiro IYOMASA, Kazuya YAMAMOTO