Patents by Inventor Hidehiko Karasaki
Hidehiko Karasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11688641Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.Type: GrantFiled: May 22, 2020Date of Patent: June 27, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidefumi Saeki, Hidehiko Karasaki, Shogo Okita, Atsushi Harikai, Akihiro Itou
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Publication number: 20220406660Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer and having a plurality of element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and an individualization step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step including a step of irradiating a first laser beam, to form a first groove exposing the semiconductor layer in the dicing region, and a step of irradiating a second laser beam, with a beam center positioned outside a side wall of the first groove, to widen the first groove into the aperture.Type: ApplicationFiled: June 10, 2022Publication date: December 22, 2022Inventors: Shogo OKITA, Hidehiko KARASAKI, Hidefumi SAEKI, Atsushi HARIKAI
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Publication number: 20220402072Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer, the substrate having element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and a step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step includes a step of irradiating a first laser beam having a first pulse width, to remove the wiring layer in an edge portion of the dicing region, and a step of irradiating a second laser beam having a second pulse width which is longer than the first pulse width, to remove the wiring layer inside from the edge portion.Type: ApplicationFiled: June 10, 2022Publication date: December 22, 2022Inventors: Hidefumi SAEKI, Hidehiko KARASAKI, Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU
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Publication number: 20220384177Abstract: A method including: a step of preparing a substrate that includes a first layer having a first principal surface provided with a dicing region, and a mark, and a second principal surface, and includes a semiconductor layer; a step of covering a first region corresponding to the mark on the second principal surface, with a resist film; a step of forming a metal film on the second principal surface; a step of removing the resist film, to expose the semiconductor layer corresponding to the first region; a step of imaging the substrate, with a camera, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region on a surface of the metal film; and a step of irradiating a laser beam to the second region, to remove the metal film and expose the semiconductor layer corresponding to the second region.Type: ApplicationFiled: May 16, 2022Publication date: December 1, 2022Inventors: Hidehiko KARASAKI, Shogo OKITA
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Publication number: 20220367273Abstract: A method including: a step of preparing a substrate that includes a first layer having a dicing region and a mark, and including a semiconductor layer, and a second layer including a metal film; a step of removing the metal film, to expose the semiconductor layer corresponding to a first region that corresponds to the mark; a step of smoothing a surface of the exposed semiconductor layer; a step of imaging the substrate, with a camera sensing predetermined electromagnetic waves, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region; and a step of removing the metal film, to expose the semiconductor layer corresponding to the second region. In the smoothing step, the surface of the semiconductor layer is smoothed so as to have a surface roughness of 1/4 or less of a wavelength of the predetermined electromagnetic waves.Type: ApplicationFiled: May 2, 2022Publication date: November 17, 2022Inventors: Hidehiko KARASAKI, Shogo OKITA
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Patent number: 11319458Abstract: A protective composition contains a water-soluble polyester resin including a polyvalent carboxylic acid residue and a polyvalent alcohol residue. The polyvalent carboxylic acid residue includes: a polyvalent carboxylic acid residue having a metal sulfonate group; and a naphthalene dicarboxylic acid residue. The proportion of the polyvalent carboxylic acid residue to the polyvalent carboxylic acid residue falls within the range from 25 mol % to 70 mol %. The proportion of the naphthalene dicarboxylic acid residue to the polyvalent carboxylic acid residue falls within the range from 30 mol % to 75 mol %.Type: GrantFiled: March 9, 2020Date of Patent: May 3, 2022Assignees: GOO CHEMICAL CO., LTD., PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Teru Sakakibara, Shinya Komabiki, Koji Maeda, Hidehiko Karasaki
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Patent number: 11289428Abstract: An element chip manufacturing method including: preparing a semiconductor substrate including a first layer having a first principal surface, and a second layer having a second principal surface, the first layer provided with element regions, a dicing region, and an alignment mark, wherein the first layer includes a semiconductor layer, and the second layer includes a metal layer adjacent to the semiconductor layer; irradiating a first laser beam absorbed in the metal film and passing through the semiconductor layer, from the second principal surface side to a first region corresponding to the mark; imaging the semiconductor substrate from the second principal surface side with a camera, and then calculating a second region corresponding to the dicing region on the second principal surface; irradiating a second laser beam to the second region from the second principal surface side; and dicing the semiconductor substrate into a plurality of element chips.Type: GrantFiled: May 12, 2020Date of Patent: March 29, 2022Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kiyoshi Arita, Shogo Okita, Hidehiko Karasaki
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Publication number: 20210324226Abstract: A protective composition contains a water-soluble polyester resin including a polyvalent carboxylic acid residue and a polyvalent alcohol residue. The polyvalent carboxylic acid residue includes: a polyvalent carboxylic acid residue having a metal sulfonate group; and a naphthalene dicarboxylic acid residue. The proportion of the polyvalent carboxylic acid residue to the polyvalent carboxylic acid residue falls within the range from 25 mol % to 70 mol %. The proportion of the naphthalene dicarboxylic acid residue to the polyvalent carboxylic acid residue falls within the range from 30 mol % to 75 mol %.Type: ApplicationFiled: March 9, 2020Publication date: October 21, 2021Inventors: Teru SAKAKIBARA, Shinya KOMABIKI, Koji MAEDA, Hidehiko KARASAKI
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Patent number: 10923362Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.Type: GrantFiled: July 27, 2020Date of Patent: February 16, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Atsushi Harikai, Noriyuki Matsubara, Shogo Okita, Hidehiko Karasaki
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Patent number: 10896849Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. A method for manufacturing an element chip includes: a step of spray coating, to the first surface of the substrate, a mixture containing a water-soluble resin and an organic solvent having a higher vapor pressure than water, and drying the coated mixture at a temperature of 50° C. or less, to form a protective film; a laser grooving step of removing portions of the protective film covering the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate; and a step of removing the portions of the protective film covering the element regions. The mixture has a solid component ratio of 200 g/L or more, and droplets of the sprayed mixture have an average particle size of 12 ?m or less.Type: GrantFiled: May 30, 2019Date of Patent: January 19, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidehiko Karasaki, Shogo Okita, Noriyuki Matsubara, Hidefumi Saeki
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Publication number: 20200381304Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.Type: ApplicationFiled: May 22, 2020Publication date: December 3, 2020Inventors: Hidefumi SAEKI, Hidehiko KARASAKI, Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU
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Publication number: 20200381367Abstract: An element chip manufacturing method including: preparing a semiconductor substrate including a first layer having a first principal surface, and a second layer having a second principal surface, the first layer provided with element regions, a dicing region, and an alignment mark, wherein the first layer includes a semiconductor layer, and the second layer includes a metal layer adjacent to the semiconductor layer; irradiating a first laser beam absorbed in the metal film and passing through the semiconductor layer, from the second principal surface side to a first region corresponding to the mark; imaging the semiconductor substrate from the second principal surface side with a camera, and then calculating a second region corresponding to the dicing region on the second principal surface; irradiating a second laser beam to the second region from the second principal surface side; and dicing the semiconductor substrate into a plurality of element chips.Type: ApplicationFiled: May 12, 2020Publication date: December 3, 2020Inventors: Kiyoshi ARITA, Shogo OKITA, Hidehiko KARASAKI
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Patent number: 10843294Abstract: Provided is a laser processing apparatus comprises a stage holding a substrate, the stage being movable in a first direction, a laser beam source radiating a laser beam onto the substrate, a dust-suction duct having a first optical path extending in a second direction perpendicular to the first direction, the laser beam travelling along the first optical path thereof, and an air aspirator aspirating an air toward a direction opposite to the first direction, wherein the dust-suction duct includes a pair of air-guiding plates opposed to each other along a third direction perpendicular to the first and second directions, and wherein the pair of the air-guiding plates are configured to have a gap therebetween such that it is narrowest in an optical path region and gets wider as it is far away from the optical path region in upstream and downstream regions thereof.Type: GrantFiled: April 25, 2018Date of Patent: November 24, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidehiko Karasaki, Hidefumi Saeki
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Publication number: 20200357654Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Atsushi HARIKAI, Noriyuki MATSUBARA, Shogo OKITA, Hidehiko KARASAKI
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Patent number: 10763124Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of dicing regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a first resin and an organic solvent having a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the dicing regions, plasma-etching the substrate along the dicing regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.Type: GrantFiled: November 19, 2018Date of Patent: September 1, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Atsushi Harikai, Noriyuki Matsubara, Shogo Okita, Hidehiko Karasaki
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Patent number: 10607846Abstract: Method of manufacturing an element chip which can suppress residual debris in plasma dicing. A back surface of a semiconductor wafer is held on a dicing tape. Then, a surface of the wafer is coated with a mask that includes a water-insoluble lower mask and a water-soluble upper mask. Subsequently, an opening is formed in the mask by irradiating the mask with laser light to expose a dividing region. Then, the semiconductor wafer is caused to come into contact with water to remove the upper mask covering each of the element regions while leaving the lower layer. After that, the wafer is exposed to plasma to perform etching on the dividing region exposed from the opening until the etching reaches the back surface, thereby dicing the semiconductor wafer into a plurality of element chips. Thereafter, the lower layer mask left on the front surface of the semiconductor chips is removed.Type: GrantFiled: August 14, 2018Date of Patent: March 31, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidehiko Karasaki, Noriyuki Matsubara, Atsushi Harikai, Hidefumi Saeki
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Patent number: 10546783Abstract: Provided is a manufacturing process of an element chip, which comprises a preparing step for preparing a substrate containing element regions and dicing regions, a holding step for holding the substrate and a frame with a holding sheet, an applicating step for applying a resin material solution containing a resin constituent and a solvent on the substrate to form a coated layer containing the resin constituent and the solvent thereon, a heating step for heating the substrate held on the holding sheet through a heat shielding member shielding the frame and the holding sheet to substantially remove the solvent from the coated layer, thereby to form a resin layer, a patterning step for patterning the resin layer to expose the substrate in the dicing regions, and a dicing step for dicing the substrate into element chips by plasma-etching the substrate.Type: GrantFiled: June 14, 2018Date of Patent: January 28, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Noriyuki Matsubara, Hidehiko Karasaki
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Publication number: 20190371669Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. A method for manufacturing an element chip includes: a step of spray coating, to the first surface of the substrate, a mixture containing a water-soluble resin and an organic solvent having a higher vapor pressure than water, and drying the coated mixture at a temperature of 50° C. or less, to form a protective film; a laser grooving step of removing portions of the protective film covering the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate; and a step of removing the portions of the protective film covering the element regions. The mixture has a solid component ratio of 200 g/L or more, and droplets of the sprayed mixture have an average particle size of 12 ?m or less.Type: ApplicationFiled: May 30, 2019Publication date: December 5, 2019Inventors: Hidehiko KARASAKI, Shogo OKITA, Noriyuki MATSUBARA, Hidefumi SAEKI
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Publication number: 20190371668Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. An method for manufacturing an element chip includes: a protective film formation step of applying a mixture containing a water-soluble resin and a solvent to the first surface, to form a protective film; a laser grooving step of irradiating, with laser light, portions of the protective film covering the dividing regions, to remove these portions, and expose the first surface in the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate in the dividing regions; and a step of removing the portions of the protective film. The resin has melting point of 250° C. or more, or decomposition temperature of 450° C. or more, and the protective film has absorption coefficient of 1 abs·L/g·cm?1 or more for wavelength of the laser light.Type: ApplicationFiled: May 30, 2019Publication date: December 5, 2019Inventors: Hidehiko KARASAKI, Shogo OKITA, Noriyuki MATSUBARA, Atsushi HARIKAI
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Patent number: 10410924Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step for preparing a substrate including a semiconductor layer having first and second sides and a wiring layer on the first side thereof, the substrate having a plurality of dicing regions and element regions defined by the dicing regions, a scribing step for radiating a laser beam towards the first side of the wiring layer onto the dicing regions to form apertures exposing the semiconductor layer along the dicing regions, and a dicing step for dicing the substrate along the apertures into a plurality of the element chips, wherein the laser beam has a beam profile having a M-shaped distribution whose peripheral intensity is greater than a central intensity in a width direction of the laser beam along the dicing regions.Type: GrantFiled: January 3, 2018Date of Patent: September 10, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidehiko Karasaki, Hidefumi Saeki, Atsushi Harikai