Patents by Inventor Hidehiko Kira

Hidehiko Kira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10586770
    Abstract: An optical module includes: a substrate including a through hole, a first chip including a first heating member and disposed in the through hole, a second chip including a second heating member and bonded to a first upper surface of the substrate and a second upper surface of the first chip via bumps, and a first heat sink adhered to a lower surface of the substrate with a first adhesive and adhered to a lower surface of the first chip with a second adhesive, wherein the substrate includes a slit which is provided on a side of a first portion, to which the second chip is bonded, of the substrate with respect to the through hole, and communicates with the through hole.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: March 10, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takayoshi Matsumura, Naoaki Nakamura, Norio Kainuma, Takashi Kubota, Kenji Fukuzono, Takumi Masuyama, Yuki Hoshino, Hidehiko Kira
  • Patent number: 10444450
    Abstract: An optical module includes a substrate, a silicon photonics chip disposed in an opening of the substrate, a control chip disposed across the substrate and the silicon photonics chip, a plurality of laser diodes disposed over the silicon photonics chip, and a metallic bar in contact with each of terminals of the plurality of laser diodes and electrically coupling each of the terminals with the silicon photonics chip or the substrate.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: October 15, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Takayoshi Matsumura, Naoaki Nakamura, Kenji Fukuzono, Norio Kainuma, Takashi Kubota, Takumi Masuyama, Yuki Hoshino, Hidehiko Kira
  • Publication number: 20190157207
    Abstract: An optical module includes: a substrate including a through hole, a first chip including a first heating member and disposed in the through hole, a second chip including a second heating member and bonded to a first upper surface of the substrate and a second upper surface of the first chip via bumps, and a first heat sink adhered to a lower surface of the substrate with a first adhesive and adhered to a lower surface of the first chip with a second adhesive, wherein the substrate includes a slit which is provided on a side of a first portion, to which the second chip is bonded, of the substrate with respect to the through hole, and communicates with the through hole.
    Type: Application
    Filed: November 5, 2018
    Publication date: May 23, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Takayoshi Matsumura, Naoaki Nakamura, NORIO KAINUMA, TAKASHI KUBOTA, KENJI FUKUZONO, Takumi Masuyama, Yuki Hoshino, Hidehiko Kira
  • Patent number: 10210720
    Abstract: Electronic equipment includes: a substrate configured to include a first component, a second component, and an interconnection part that couples the first component with the second component by electric interconnections; and an exterior part configured to cover the first component, the second component, and the interconnection parts, and include a first exterior section that covers at least a portion of the first component, and a second exterior section that covers at least a portion of the interconnection parts, a thickness of the first exterior section being different from a thickness of the second exterior section to form a level difference in a boundary part between the first exterior section and the second exterior section.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: February 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Takayoshi Matsumura, Shunji Baba, Takashi Kanda, Noritsugu Ozaki, Hidehiko Kira
  • Publication number: 20180341075
    Abstract: An optical module includes a substrate, a silicon photonics chip disposed in an opening of the substrate, a control chip disposed across the substrate and the silicon photonics chip, a plurality of laser diodes disposed over the silicon photonics chip, and a metallic bar in contact with each of terminals of the plurality of laser diodes and electrically coupling each of the terminals with the silicon photonics chip or the substrate.
    Type: Application
    Filed: May 22, 2018
    Publication date: November 29, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Takayoshi Matsumura, Naoaki Nakamura, KENJI FUKUZONO, NORIO KAINUMA, TAKASHI KUBOTA, Takumi Masuyama, Yuki Hoshino, Hidehiko Kira
  • Patent number: 10115694
    Abstract: An electronic device includes an electronic part including a first substrate having a group of first terminals over a first front surface and having a concavity in a back surface, a filler placed in the concavity, and a flat plate placed over the back surface with the filler therebetween, and further includes a second substrate disposed on the first front surface side of the first substrate and having a group of second terminals bonded to the group of first terminals over a second front surface opposite the first front surface. The filler and flat plate minimize deformation of the first substrate and variation in the distance between the group of first terminals and the group of second terminals caused by the deformation of the first substrate, which thereby reduces the occurrence of a failure in bonding together the group of first terminals and the group of second terminals.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: October 30, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Hidehiko Kira, Naoaki Nakamura, Sanae Iijima
  • Patent number: 10103126
    Abstract: A laminated semiconductor device includes: three or more semiconductor chips that are laminated; resins that are disposed among the semiconductor chips, the resins softening by heating; and support members that are disposed among the semiconductor chips and that contacts the adjacent semiconductor chips, the support members deforming by external force when a temperature of the support members reaching a predetermined temperature.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 16, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Hidehiko Kira, Norio Kainuma
  • Publication number: 20180217343
    Abstract: An optical module includes a housing; a substrate configured to have a through hole; a first chip configured to have a first heating member and be disposed inside the through hole; a second chip configured to have a second heating member, the second chip being placed on the substrate and the first chip with a bump interposed; a first heat conduction member configured to be sandwiched between a lower wall of the housing and the first chip and transfer heat generated by the first heating member to the lower wall of the housing; and a second heat conduction member configured to be sandwiched between an upper wall of the housing and the second chip and transfer heat generated by the second heating member to the upper wall of the housing.
    Type: Application
    Filed: January 19, 2018
    Publication date: August 2, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Takayoshi Matsumura, Naoaki Nakamura, NORIO KAINUMA, KENJI FUKUZONO, Yuki Hoshino, TAKASHI KUBOTA, Takumi Masuyama, Hidehiko Kira
  • Patent number: 9905528
    Abstract: A semiconductor mounting apparatus includes a storing unit that stores a liquid or a gas, a contact unit that comes into contact with a semiconductor chip when the storing unit is filled with the liquid or the gas, and a sucking unit that sucks up the semiconductor chip to bring the semiconductor chip into close contact with the contact unit.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: February 27, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Hidehiko Kira, Takumi Masuyama
  • Publication number: 20180035536
    Abstract: A wiring board includes a base having extensibility and a wiring formed on the base. The wiring includes a wiring portion and a conductor portion. The wiring portion is formed on the base and extends in a first direction crossing (for example, perpendicular to) a longitudinal direction of the base. The conductor portion is formed on the wiring portion and extends in the first direction. Even when the wiring board is extended along a main extension axis in parallel with the longitudinal direction of the base, change of the resistance of the wiring is prevented. Thus, the wiring board represents stable characteristics.
    Type: Application
    Filed: June 14, 2017
    Publication date: February 1, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Takayoshi Matsumura, Shunji Baba, TAKASHI KANDA, NORITSUGU OZAKI, Hidehiko Kira
  • Publication number: 20170345264
    Abstract: Electronic equipment includes: a substrate configured to include a first component, a second component, and an interconnection part that couples the first component with the second component by electric interconnections; and an exterior part configured to cover the first component, the second component, and the interconnection parts, and include a first exterior section that covers at least a portion of the first component, and a second exterior section that covers at least a portion of the interconnection parts, a thickness of the first exterior section being different from a thickness of the second exterior section to form a level difference in a boundary part between the first exterior section and the second exterior section.
    Type: Application
    Filed: May 2, 2017
    Publication date: November 30, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Takayoshi Matsumura, Shunji Baba, TAKASHI KANDA, NORITSUGU OZAKI, Hidehiko Kira
  • Patent number: 9793221
    Abstract: A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 17, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hidehiko Kira, Norio Kainuma, Takashi Kubota, Takumi Masuyama
  • Publication number: 20170207199
    Abstract: A laminated semiconductor device includes: three or more semiconductor chips that are laminated; resins that are disposed among the semiconductor chips, the resins softening by heating; and support members that are disposed among the semiconductor chips and that contacts the adjacent semiconductor chips, the support members deforming by external force when a temperature of the support members reaching a predetermined temperature.
    Type: Application
    Filed: January 3, 2017
    Publication date: July 20, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Hidehiko Kira, NORIO KAINUMA
  • Publication number: 20170186718
    Abstract: An electronic device includes an electronic part including a first substrate having a group of first terminals over a first front surface and having a concavity in a back surface, a filler placed in the concavity, and a flat plate placed over the back surface with the filler therebetween, and further includes a second substrate disposed on the first front surface side of the first substrate and having a group of second terminals bonded to the group of first terminals over a second front surface opposite the first front surface. The filler and flat plate minimize deformation of the first substrate and variation in the distance between the group of first terminals and the group of second terminals caused by the deformation of the first substrate, which thereby reduces the occurrence of a failure in bonding together the group of first terminals and the group of second terminals.
    Type: Application
    Filed: December 5, 2016
    Publication date: June 29, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Hidehiko Kira, Naoaki Nakamura, Sanae IIJIMA
  • Publication number: 20170186719
    Abstract: A semiconductor device includes a first substrate, a second substrate, a connection portion, and resin. The second substrate faces the first substrate, and has a recess at a position corresponding to an edge portion of the first substrate. The connection portion is interposed between the first substrate and the second substrate, and electrically connects the first substrate and the second substrate. Resin is disposed to remain between the first substrate and the second substrate, and covers the connection portion. Part of the resin is present in the recess of the second substrate. The recess serves as a resin reservoir for resin that is caused to flow upon bonding, and prevents the resin from flowing along a side surface of the first substrate to a back surface thereof, thereby preventing contamination by the resin.
    Type: Application
    Filed: December 5, 2016
    Publication date: June 29, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Hidehiko Kira, Naoaki Nakamura, TAKASHI KUBOTA
  • Publication number: 20170186721
    Abstract: A semiconductor mounting apparatus includes a storing unit that stores a liquid or a gas, a contact unit that comes into contact with a semiconductor chip when the storing unit is filled with the liquid or the gas, and a sucking unit that sucks up the semiconductor chip to bring the semiconductor chip into close contact with the contact unit.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 29, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Hidehiko Kira, Takumi Masuyama
  • Patent number: 9615464
    Abstract: A method of mounting a semiconductor element, the method includes: attaching a first solder joint material onto a first pad formed on a substrate supplying a second solder joint material onto the first solder joint material, a second melting point of the second solder joint material being lower than a first melting point of the first solder joint material; arranging the semiconductor element so that a second pad formed on the semiconductor element faces the first pad and a joint gap is provided between the semiconductor element and the substrate; and performing reflow at a reflow temperature lower than the first melting point and higher than the second melting point to join the first solder joint material and the second solder joint material.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: April 4, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Kubota, Masayuki Kitajima, Takatoyo Yamakami, Hidehiko Kira
  • Patent number: 9547126
    Abstract: An optical waveguide sheet, includes: an optical path; and a clad member that covers the optical path, wherein the clad member has a portion formed by removing a part of the clad member which is on a first surface of an optical waveguide sheet on which the optical component is to be mounted and is provided within an area which is unused for propagation of light input to and output from the optical component.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 17, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Sanae Iijima, Takashi Kubota, Norio Kainuma, Hidehiko Kira
  • Patent number: 9536857
    Abstract: A heating header of a semiconductor mounting apparatus includes: a first material; and a second material, the second material being bonded to the first material and coming into contact with a first semiconductor chip when the first semiconductor chip is compressed, wherein a contact surface of the second material with the first semiconductor chip is a curved surface that is convex toward the first semiconductor chip side, and the contact surface of the second material with the first semiconductor chip becomes a planar surface when each temperature of the first material and the second material reaches a melting temperature of a solder that is formed between a first terminal of the first semiconductor chip and a second terminal of a second semiconductor chip.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 3, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hidehiko Kira, Takumi Masuyama, Norio Kainuma
  • Publication number: 20160284566
    Abstract: A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.
    Type: Application
    Filed: January 29, 2016
    Publication date: September 29, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Hidehiko Kira, NORIO KAINUMA, TAKASHI KUBOTA, Takumi Masuyama