Patents by Inventor Hidehiko Shiraiwa
Hidehiko Shiraiwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11183509Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: GrantFiled: June 18, 2020Date of Patent: November 23, 2021Assignee: Cypress Semiconductor CorporationInventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Publication number: 20200411537Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: ApplicationFiled: June 18, 2020Publication date: December 31, 2020Applicant: Infineon Technologies LLCInventors: Ching-Huang LU, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Patent number: 10692877Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: GrantFiled: April 17, 2017Date of Patent: June 23, 2020Assignee: Cypress Semiconductor CorporationInventors: Ching-Huang Lu, Simon S. Chan, Hidehiko Shiraiwa, Lei Xue
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Patent number: 10622370Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: GrantFiled: September 25, 2015Date of Patent: April 14, 2020Assignee: Monterey Research, LLCInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, Youseok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Ramesh Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Publication number: 20170250192Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: ApplicationFiled: April 17, 2017Publication date: August 31, 2017Applicant: Cypress Semiconductor CorporationInventors: Ching-Huang LU, Simon S. Chan, Hidehiko Shiraiwa, Lei Xue
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Patent number: 9666591Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: GrantFiled: January 26, 2016Date of Patent: May 30, 2017Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Patent number: 9431503Abstract: An integrated circuit comprises a first poly-silicon region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a first poly-silicon finger associated with the first poly-silicon layer, and a second poly-silicon finger associated with the second poly-silicon layer. The first poly-silicon finger and the second poly-silicon finger are oriented in a substantially orthogonal manner relative to each other. The integrated circuit comprises a second poly-silicon gate region including the first poly-silicon layer. The first polysilicon gate region and the second polysilicon gate region each have different poly-silicon gate structures.Type: GrantFiled: January 7, 2014Date of Patent: August 30, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Chuan Lin, Hidehiko Shiraiwa, Bradley Marc Davis, Lei Xue, Simon S. Chan, Kenichi Ohtsuka, Angela T. Hui, Scott Allan Bell
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Publication number: 20160211271Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: ApplicationFiled: January 26, 2016Publication date: July 21, 2016Inventors: Ching-Huang LU, Simon Siu-Sing CHAN, Hidehiko Shiraiwa, Lei Xue
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Patent number: 9276007Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: GrantFiled: January 29, 2014Date of Patent: March 1, 2016Assignee: Cypress Semiconductor CorporationInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Patent number: 9252154Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: GrantFiled: September 30, 2014Date of Patent: February 2, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Patent number: 9196624Abstract: Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.Type: GrantFiled: July 10, 2012Date of Patent: November 24, 2015Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Bradley Marc Davis, Mark W. Randolph, Sung-Yong Chung, Hidehiko Shiraiwa
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Patent number: 9111985Abstract: A shallow bipolar junction transistor comprising a high voltage n+ well implanted into a semiconductor substrate. The shallow bipolar junction transistor further comprises a bit line n+ implant (BNI) above the high voltage n+ well and an oxide nitride (ONO) layer above the high voltage n+ well. A portion of the ONO layer isolates the BNI from a shallow trench isolation (STI) region.Type: GrantFiled: January 11, 2007Date of Patent: August 18, 2015Assignee: Cypress Semiconductor CorporationInventors: Alok Nandini Roy, Gulzar Kathawala, Zubin Patel, Hidehiko Shiraiwa
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Publication number: 20150017795Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Publication number: 20140312409Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: ApplicationFiled: January 29, 2014Publication date: October 23, 2014Applicant: SPANSION LLCInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Patent number: 8866213Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: GrantFiled: January 30, 2013Date of Patent: October 21, 2014Assignee: Spansion LLCInventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Patent number: 8809936Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.Type: GrantFiled: July 31, 2006Date of Patent: August 19, 2014Assignees: Globalfoundries Inc., Spansion LLCInventors: Lei Xue, Rinji Sugino, YouSeok Suh, Hidehiko Shiraiwa, Meng Ding, Shenqing Fang, Joong Jeon
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Publication number: 20140209993Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A farther benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Applicant: Spansion LLCInventors: Ching-Huang LU, Simon Siu-Sing CHAN, Hidehiko SHIRAIWA, Lei XUE
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Publication number: 20140117435Abstract: A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.Type: ApplicationFiled: January 7, 2014Publication date: May 1, 2014Applicant: Spansion LLCInventors: Chuan LIN, Hidehiko Shiraiwa, Bradley Marc Davis, Lei Xue, Simon S. Chan, Kenichi Ohtsuka, Angela T. Hui, Scott Allan Bell
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Patent number: 8673716Abstract: A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.Type: GrantFiled: April 8, 2002Date of Patent: March 18, 2014Assignee: Spansion LLCInventors: Mark T. Ramsbey, Tazrien Kamal, Jean Y. Yang, Emmanuil Lingunis, Hidehiko Shiraiwa, Yu Sun
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Patent number: 8652907Abstract: A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.Type: GrantFiled: March 24, 2011Date of Patent: February 18, 2014Assignee: Spansion LLCInventors: Chuan Lin, Hidehiko Shiraiwa, Bradley Marc Davis, Lei Xue, Simon S. Chan, Kenichi Ohtsuka, Angela T. Hui, Scott Allan Bell