Patents by Inventor Hidehiko Tachibana

Hidehiko Tachibana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090261867
    Abstract: Input and output nodes, an output circuit and a drive circuit are provided. The output circuit includes first and second n-channel MOS transistors connected to each other in series. A drain of the first n-channel MOS transistor is connected to a first line. A source of the first n-channel MOS transistor, a drain of the second n-channel MOS transistor, and a drain of a first p-channel MOS transistor are commonly connected to the output node. A source of the second n-channel MOS transistor is connected to a second line. A source of the first p-channel MOS transistor is connected to the first line. The drive circuit generates first to third control signals in response to an input signal provided to the input node. The control signals are respectively outputted to gates of the first and second n-channel MOS transistors and to a gate of the first p-channel MOS transistor.
    Type: Application
    Filed: April 16, 2009
    Publication date: October 22, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kumio Gundo, Hidehiko Tachibana, Kouji Nakashima
  • Publication number: 20080136798
    Abstract: A liquid-crystal display device comprises a liquid-crystal panel having liquid-crystal display elements at intersections of a plurality of address lines and a plurality of signal lines, a signal line driver circuit configured to drive the signal line at an image signal voltage, and an address line driver circuit configured to drive the address line by a display control signal and having a control function of switching directions in which the display control signal is transferred. The address line driver circuit includes a shift register configured to take in the display control signal, a switching circuit configured to switch directions in which the display control signal is transferred in the shift register, and a setting circuit configured to set a direction in which the display control signal is taken in.
    Type: Application
    Filed: December 5, 2007
    Publication date: June 12, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keisuke Ashida, Hidehiko Tachibana, Satoshi Suzuki
  • Patent number: 6043812
    Abstract: Output circuits OC1-OC240 supplied with picture signals VIN to output drive signals are provided. Each of the output circuits OC includes a switching element SW1, a capacitor C1 and a switching element SW2 provided at a first path, and a switching element SW3, a capacitor C2 and a switching element SW4 provided at a second path connected in parallel with the first path, and includes a sample-hold circuit SH1 supplied with a picture signal and a hold switching signal of which level is switched at a first period to alternately store the picture signal into the capacitor C1 or the capacitor C2 in accordance with hold switching signal to output it, and an amplifier AMP1 supplied with an output of this circuit SH1 to amplify that output to output it as a drive signal. Further, buffers are provided every output circuits OC. These buffers are connected to each other in series. Hold switching signal inputted from the external is inputted to the buffers and are propagated therethrough.
    Type: Grant
    Filed: April 1, 1998
    Date of Patent: March 28, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takanori Utsunomiya, Hidehiko Tachibana
  • Patent number: 5933043
    Abstract: In a level shift circuit having a bias circuit and an output circuit, the current consumption of the bias circuit can be suppressed, and further the delay of the output signal relative to the input signal can be reduced. The ratio circuit comprises a bias circuit block (5) composed of a transistor (1) connected to a high potential power source (7) and having a gate to which an input bias INBIAS is applied through a bias input terminal (11), a transistor (2) connected in series to the transistor (1) so as to function as a resistance, and a transistor (13) connected in series to the transistor (2) and a low potential power source (8); and an output circuit block (6) composed of a transistor (3) connected to the high potential power source (7) and having a gate to which an input signal IN is applied through an input terminal (10) and a drain from which an output signal OUT is derived to an output terminal (12), and a transistor (4) connected in series to the transistor (3) and a low potential power source (8).
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: August 3, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takanori Utsunomiya, Hidehiko Tachibana
  • Patent number: 5587683
    Abstract: A booster circuit device comprises: a liquid crystal drive circuit (14) whose dissipated current changes; a timing circuit (11) for outputting a select signal according to the dissipated current of the liquid crystal drive circuit; a drive signal select circuit (12) for selecting and outputting any one of at least two drive signals CLK of different frequencies on the basis of the select signal outputted by the timing circuit (11); and a booster circuit (13) for supplying a supply voltage to the liquid crystal drive circuit (14) on the basis of the drive signal CLK outputted by the drive signal select circuit (12). Since any of the drive signals CLK of different frequencies can be selected and applied to the booster circuit (13) according to the dissipated current of the liquid crystal drive circuit (14), it is possible to reduce the current dissipation of the booster circuit, that is the current dissipation of the whole booster circuit device can be reduced markedly.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: December 24, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Kawasaki, Yasunori Kuwasima, Hidehiko Tachibana, Syuji Katsuki, Akihiro Sueda