Abstract: There is a provided a drive circuit including a power supply voltage control circuit that controls supply of a power supply voltage to a first device and a second device, a first drive signal output circuit that includes a first detection circuit detecting a voltage value of the power supply voltage, and outputs a first drive signal, a second drive signal output circuit that includes a second detection circuit detecting the voltage value of the power supply voltage, and outputs a second drive signal, a first fuse having one end electrically coupled to a first detection circuit and a first selection circuit, and the other end electrically coupled to the power supply voltage control circuit, and a second fuse having one end electrically coupled to a second detection circuit and a second selection circuit, and the other end electrically coupled to the power supply voltage control circuit.

Abstract: There is a provided a drive circuit in which a first drive signal output circuit includes a first control circuit that controls an output of a first drive signal, and a first abnormality detection circuit that detects an abnormality in a first drive signal output circuit, a second drive signal output circuit includes a second control circuit that controls an output of a second drive signal, and a second abnormality detection circuit that detects an abnormality in a second drive signal output circuit, the first drive signal output circuit transmits an occurrence of abnormality to the second drive signal output circuit, when the first abnormality detection circuit detects the abnormality, and the second drive signal output circuit transmits an occurrence of abnormality to the first drive signal output circuit, when the second abnormality detection circuit detects the abnormality.

Abstract: There is a provided a drive circuit in which a first drive signal output circuit includes a first control circuit that controls an output of a first drive signal, and a first abnormality detection circuit that detects an abnormality in a first drive signal output circuit, a second drive signal output circuit includes a second control circuit that controls an output of a second drive signal, and a second abnormality detection circuit that detects an abnormality in a second drive signal output circuit, the first drive signal output circuit transmits an occurrence of abnormality to the second drive signal output circuit, when the first abnormality detection circuit detects the abnormality, and the second drive signal output circuit transmits an occurrence of abnormality to the first drive signal output circuit, when the second abnormality detection circuit detects the abnormality.

Abstract: There is a provided a drive circuit including a power supply voltage control circuit that controls supply of a power supply voltage to a first device and a second device, a first drive signal output circuit that includes a first detection circuit detecting a voltage value of the power supply voltage, and outputs a first drive signal, a second drive signal output circuit that includes a second detection circuit detecting the voltage value of the power supply voltage, and outputs a second drive signal, a first fuse having one end electrically coupled to a first detection circuit and a first selection circuit, and the other end electrically coupled to the power supply voltage control circuit, and a second fuse having one end electrically coupled to a second detection circuit and a second selection circuit, and the other end electrically coupled to the power supply voltage control circuit.

Abstract: There is provided a liquid discharge apparatus including: a discharge unit which discharges a liquid by a piezoelectric element; and a driving circuit which drives the piezoelectric element, in which the driving circuit includes a first transistor pair which is driven by a first power source voltage and a second power source voltage, a second transistor pair which is driven by the second power source voltage and a third power source voltage, and a first control circuit which controls on a first input signal, and in which, the shortest distance between the first power source voltage and the first input terminal is shorter than the shortest distance between the second power source voltage and the first input terminal, and the shortest distance between the second power source terminal and the first input terminal is shorter than the shortest distance between the third power source voltage and the first input terminal.

Abstract: An input protection circuit changes the voltage of a signal to be input to an input circuit to a predetermined voltage or less and outputs the signal. The input protection circuit includes a first NMOS transistor and a second NMOS transistor. The the first NMOS transistor includes a source to which an input signal is input, a gate to which a voltage based on a first voltage is applied, and a drain that outputs the signal to the input circuit based on the input signal and the gate voltage. The second NMOS transistor includes a source and a gate to each of which the voltage based on the first voltage is applied, and a drain that outputs a second voltage to the input circuit.

Abstract: There is provided a liquid discharge apparatus including: a discharge unit which discharges a liquid by a piezoelectric element; and a driving circuit which drives the piezoelectric element, in which the driving circuit includes a first transistor pair which is driven by a first power source voltage and a second power source voltage, a second transistor pair which is driven by the second power source voltage and a third power source voltage, and a first control circuit which controls on a first input signal, and in which, the shortest distance between the first power source voltage and the first input terminal is shorter than the shortest distance between the second power source voltage and the first input terminal, and the shortest distance between the second power source terminal and the first input terminal is shorter than the shortest distance between the third power source voltage and the first input terminal.

Abstract: An input protection circuit changes the voltage of a signal to be input to an input circuit to a predetermined voltage or less and outputs the signal. The input protection circuit includes a first NMOS transistor and a second NMOS transistor. The the first NMOS transistor includes a source to which an input signal is input, a gate to which a voltage based on a first voltage is applied, and a drain that outputs the signal to the input circuit based on the input signal and the gate voltage. The second NMOS transistor includes a source and a gate to each of which the voltage based on the first voltage is applied, and a drain that outputs a second voltage to the input circuit.

Abstract: An input protection circuit changes the voltage of a signal to be input to an input circuit to a predetermined voltage or less and outputs the signal. The input protection circuit includes a first NMOS transistor and a second NMOS transistor. The first NMOS transistor includes a source to which an input signal is input, a gate to which a voltage based on a first voltage is applied, and a drain that outputs the signal to the input circuit based on the input signal and the gate voltage. The second NMOS transistor includes a source and a gate to each of which the voltage based on the first voltage is applied, and a drain that outputs a second voltage to the input circuit.

Abstract: An input protection circuit changes the voltage of a signal to be input to an input circuit to a predetermined voltage or less and outputs the signal. The input protection circuit includes a first NMOS transistor and a second NMOS transistor. The first NMOS transistor includes a source to which an input signal is input, a gate to which a voltage based on a first voltage is applied, and a drain that outputs the signal to the input circuit based on the input signal and the gate voltage. The second NMOS transistor includes a source and a gate to each of which the voltage based on the first voltage is applied, and a drain that outputs a second voltage to the input circuit.

Abstract: A display device includes an integrated circuit device and a display panel. The display panel includes a panel test terminal that is used to test the display panel, and a driver output terminal that is electrically connected with a data driver pad of the integrated circuit device and is electrically connected with the panel test terminal. The integrated circuit device includes a data driver block and a high-speed I/F circuit block including a physical layer circuit. The physical layer circuit is disposed in the integrated circuit device so that the physical layer circuit non-overlaps a predetermined test terminal region, the predetermined test terminal region being a region in which the panel test terminal is predetermined to locate under the integrated circuit device when the integrated circuit device is mounted on the display panel.

Abstract: An integrated circuit device includes a scan driver block, a high-speed interface circuit block, and a scan driver pad arrangement region in which pads electrically connecting scan output lines of the scan driver block and scan lines are disposed. The high-speed interface circuit block includes a physical layer circuit that receives data using differential signals, and a link controller that performs a link layer process. The scan output lines of the scan driver block are provided from the scan driver block to the scan driver pad arrangement region to pass over the link controller while avoiding the physical layer circuit. A common voltage line connecting first and second common voltage pads is provided from the first common voltage pad to the second common voltage pad along a first direction, the common voltage line being provided in a second direction with respect to the physical layer circuit along the first direction in an arrangement region of the physical layer circuit.

Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. A first-conductivity-type transistor included in the high-speed I/F circuit block is formed in a second-conductivity-type well, and a second-conductivity-type transistor included in the high-speed I/F circuit block is formed in a first-conductivity-type well formed in a second-conductivity-type substrate to enclose the second-conductivity-type well. A first-conductivity-type transistor and a second-conductivity-type transistor included in the driver logic circuit block are formed in a region other than a region of the first-conductivity-type well for the high-speed interface circuit block.

Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. The high-speed I/F circuit block includes a physical layer circuit including a receiver circuit, and a high-speed I/F logic circuit including a serial/parallel conversion circuit. The high-speed I/F circuit block is disposed so that the high-speed I/F logic circuit is disposed between the physical layer circuit and the driver logic circuit block and the physical layer circuit and the driver logic circuit block are not adjacently disposed.

Abstract: A display device includes an integrated circuit device and a display panel. The display panel includes a panel test terminal that is used to test the display panel, and a driver output terminal that is electrically connected with a data driver pad of the integrated circuit device and is electrically connected with the panel test terminal. The integrated circuit device includes a data driver block and a high-speed I/F circuit block including a physical layer circuit. The physical layer circuit is disposed in the integrated circuit device so that the physical layer circuit non-overlaps a predetermined test terminal region, the predetermined test terminal region being a region in which the panel test terminal is predetermined to locate under the integrated circuit device when the integrated circuit device is mounted on the display panel.

Abstract: An integrated circuit device includes a scan driver block, a high-speed interface circuit block, and a scan driver pad arrangement region in which pads electrically connecting scan output lines of the scan driver block and scan lines are disposed. The high-speed interface circuit block includes a physical layer circuit that receives data using differential signals, and a link controller that performs a link layer process. The scan output lines of the scan driver block are provided from the scan driver block to the scan driver pad arrangement region to pass over the link controller while avoiding the physical layer circuit. A common voltage line connecting first and second common voltage pads is provided from the first common voltage pad to the second common voltage pad along a first direction, the common voltage line being provided in a second direction with respect to the physical layer circuit along the first direction in an arrangement region of the physical layer circuit.

Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. The high-speed I/F circuit block includes a physical layer circuit including a receiver circuit, and a high-speed I/F logic circuit including a serial/parallel conversion circuit. The high-speed I/F circuit block is disposed so that the high-speed I/F logic circuit is disposed between the physical layer circuit and the driver logic circuit block and the physical layer circuit and the driver logic circuit block are not adjacently disposed.

Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. A first-conductivity-type transistor included in the high-speed I/F circuit block is formed in a second-conductivity-type well, and a second-conductivity-type transistor included in the high-speed I/F circuit block is formed in a first-conductivity-type well formed in a second-conductivity-type substrate to enclose the second-conductivity-type well. A first-conductivity-type transistor and a second-conductivity-type transistor included in the driver logic circuit block are formed in a region other than a region of the first-conductivity-type well for the high-speed interface circuit block.

Abstract: A driver IC, which is mounted on an active matrix substrate by means of COG, is provided. The driver IC includes an input-output circuit, an internal circuit region having a plurality of internal circuits, a plurality of substrate-coupling bumps coupled to the input-output circuit, and at least one dummy bump. The dummy bump is placed facing opposite to one of the plurality of internal circuits which becomes an object of light shielding.

Abstract: The invention provides a semiconductor integrated circuit that can be used as either a segment driver or a common driver, where the number of wires for scanning data is reduced so that the area of the wiring is reduced and the layout is simplified. The semiconductor integrated circuit includes: a plurality of data holding devices that each hold data that is inputted via a first terminal and output the data to a second terminal or hold data that is inputted via the second terminal and output the data to the first terminal in response to the operating mode and the scanning direction; a switching device that switches the connections of the plurality of data holding devices in response to the operating mode; and a plurality of selecting devices that select one out of data outputted from the terminals of the plurality of data holding devices and data outputted from the terminals of the plurality of data holding devices in response to the operating mode and the scanning direction.