Patents by Inventor Hidehiko Yamashita

Hidehiko Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10620359
    Abstract: A lighting device includes a light source, a light guide plate, an optical sheet, and a light blocking member. The light guide plate includes a section of a peripheral surface opposed to the light source defined as a light entering surface, a section of the peripheral surface opposite from the light entering surface defined as an opposite surface, and a light exiting plate surface through which light exits. The optical sheet is disposed over the light exiting plate surface. The light blocking member is in an outer edge area of at least one of the light guide plate and the optical sheet to block the light from the light guide plate through the light exiting plate surface. The light blocking member extends in a peripheral direction along the peripheral surface in which the light entering surface and the opposite surface are arranged.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 14, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Hidehiko Yamashita
  • Publication number: 20190101683
    Abstract: A lighting device includes a light source, a light guide plate, an optical sheet, and a light blocking member. The light guide plate includes a section of a peripheral surface opposed to the light source defined as a light entering surface, a section of the peripheral surface opposite from the light entering surface defined as an opposite surface, and a light exiting plate surface through which light exits. The optical sheet is disposed over the light exiting plate surface. The light blocking member is in an outer edge area of at least one of the light guide plate and the optical sheet to block the light from the light guide plate through the light exiting plate surface. The light blocking member extends in a peripheral direction along the peripheral surface in which the light entering surface and the opposite surface are arranged.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 4, 2019
    Inventor: Hidehiko YAMASHITA
  • Patent number: 7978169
    Abstract: There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: July 12, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidehiko Yamashita, Hajime Washio, Yasushi Kubota, Graham Andrew Cairns, Michael James Brownlow
  • Publication number: 20080150924
    Abstract: There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.
    Type: Application
    Filed: February 21, 2008
    Publication date: June 26, 2008
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hidehiko Yamashita, Hajime Washio, Yasushi Kubota, Graham Andrew Cairns, Michael James Brownlow
  • Patent number: 7358950
    Abstract: There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: April 15, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidehiko Yamashita, Hajime Washio, Yasushi Kubota, Graham Andrew Cairns, Michael James Brownlow
  • Patent number: 7167151
    Abstract: Each of a plurality of source lines is connected to a video signal line via an analog switch and a read-out switch, which are turned ON/OFF by a source line driving circuit. When the analog switch of the source line is turned ON and the read-out switch thereof is turned OFF, the selected source line is connected to the video signal line, thereby writing a video signal to a storage capacitor of a picture element via a picture element transistor. When the analog switch of the source line is turned OFF and the read-out switch thereof is turned ON, a signal stored in a storage capacitor is read out from the source line to the read-out line via the picture element transistor. The read-out line is a single line shared by the plurality of source lines.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: January 23, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hidehiko Yamashita
  • Publication number: 20030151587
    Abstract: Each of a plurality of source lines is connected to a video signal line via an analog switch and a read-out switch, which are turned ON/OFF by a source line driving circuit. When the analog switch of the source line is turned ON and the read-out switch thereof is turned OFF, the selected source line is connected to the video signal line, thereby writing a video signal to a storage capacitor of a picture element via a picture element transistor. When the analog switch of the source line is turned OFF and the read-out switch thereof is turned ON, a signal stored in a storage capacitor is read out from the source line to the read-out line via the picture element transistor. The read-out line is a single line shared by the plurality of source lines.
    Type: Application
    Filed: February 10, 2003
    Publication date: August 14, 2003
    Inventor: Hidehiko Yamashita
  • Patent number: 6556162
    Abstract: A digital-to-analog converter includes a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit including switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during the precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: April 29, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michael James Brownlow, Graham Andrew Cairns, Catherine Rosinda Marie Armida Dachs, Hidehiko Yamashita, Yasushi Kubota, Hajime Washio
  • Publication number: 20020180722
    Abstract: There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.
    Type: Application
    Filed: May 16, 2002
    Publication date: December 5, 2002
    Inventors: Hidehiko Yamashita, Hajime Washio, Yasushi Kubota, Graham Andrew Cairns, Michael James Brownlow
  • Publication number: 20020041245
    Abstract: A digital-to-analog converter comprises a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit comprising switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during a precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.
    Type: Application
    Filed: May 2, 2001
    Publication date: April 11, 2002
    Inventors: Michael James Brownlow, Graham Andrew Cairns, Catherine Rosinda Marie Armida Dachs, Hidehiko Yamashita, Yasushi Kubota, Hajime Washio
  • Patent number: 5936291
    Abstract: The thin film transistor of this invention is formed on a substrate and includes an active layer and a first insulating film and a second insulating film sandwiching the active layer, wherein the overall polarity of fixed charges contained in the first insulating film is the reverse of the overall polarity of fixed charges contained in the second insulating film.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: August 10, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoki Makita, Muneyuki Motohashi, Hidehiko Yamashita, Hideo Izawa
  • Patent number: 5760853
    Abstract: A liquid crystal light valve includes a transparent substrate having a transparent electrode, a photoconducting layer and a dielectric mirror layer including a plurality of dielectric films formed in this order on a surface thereof, a transparent substrate having a transparent electrode formed on a surface thereof, and a liquid crystal layer held between the transparent substrates. The dielectric mirror layer includes a high packing density portion as the outermost layer on the liquid crystal layer side, and a low packing density portion with a packing density lower than that of the high packing density portion. This structure improves the optical characteristic and the manufacturing efficiency of the liquid crystal light valve.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: June 2, 1998
    Assignee: Sharp, Kabushiki Kaisha
    Inventor: Hidehiko Yamashita
  • Patent number: 5467204
    Abstract: A liquid crystal light valve and a various information processors is provided. The processors have the liquid crystal light valve in which information formed in a liquid crystal layer and corresponding to address light can be read as an optical signal and can be directly read as an electric signal.A liquid crystal light valve has a glass substrate, an antireflection film, a transparent electrode, an opposite electrode, an optical waveguide, a photoconductive layer, a light interrupting layer, an orientational film, a spacer and a liquid crystal layer. The optical waveguide is composed of a lower clad layer, a core layer and a clad layer. A light source and a photodetector are connected to both ends of the optical waveguide. For example, the light source is constructed by a laser, a light emitting diode (LED), etc. The light source is connected to the optical waveguide such that a polarized wave can be guided to the optical waveguide.
    Type: Grant
    Filed: December 9, 1992
    Date of Patent: November 14, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akitsugu Hatano, Tsuyoshi Okazaki, Yukihiro Sumida, Takashi Nojima, Hidehiko Yamashita
  • Patent number: 5307186
    Abstract: A liquid crystal light valve includes a first substrate having a transparent electrode formed thereon, a second substrate, a liquid crystal provided between the first and second substrates, a photoconductive layer formed between the liquid crystal layer and the first substrate, the photoconductive layer being adapted to change impedance thereof in response to an incident ray of light thereto, and a light waveguide for emitting light from the first substrate side to the photoconductive layer.
    Type: Grant
    Filed: July 31, 1992
    Date of Patent: April 26, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Tsuyoshi Okazaki, Hidehiko Yamashita, Akitsugu Hatano