Abstract: A solid-state imaging device efficiently using a three-dimensional transistor. A solid-state imaging device includes a pixel circuit, a pixel array, a first signal line, and a first signal processing circuit. The pixel circuit outputs a signal based on intensity of light received by a light receiving element. In the pixel array, the pixel circuit is arranged in a two-dimensional array in a first direction and a second direction intersecting the first direction. The first signal line is connected to the pixel circuit continuous in the second direction. The first signal processing circuit performs signal processing on a signal from the pixel circuit output from a plurality of the signal lines. Each of at least one transistor in the pixel circuit and at least one transistor in the first signal processing circuit is a three-dimensional transistor.

Abstract: To improve charge transfer efficiency in a solid-state imaging device that transfers a charge from a photoelectric conversion element to a floating diffusion layer. A solid-state imaging device is provided with a transfer transistor and a potential control unit. In this solid-state imaging device, the transfer transistor transfers a charge from a photoelectric conversion element to a floating diffusion layer in a predetermined transfer period according to a transfer signal transmitted through a predetermined transfer line. Furthermore, the potential control unit makes a potential in a transfer period of a predetermined signal line capacitively coupled with the floating diffusion layer higher than that outside the transfer period.

Abstract: Coexistence of the realization of high-capacity of a capacitive element and the area reduction of a semiconductor device is aimed at. A plurality of capacitive elements from which a kind differs mutually are accumulated and arranged on a semiconductor substrate, and they are connected in parallel. These capacitive elements are arranged to the same plane region, and make a plane size almost the same. A lower capacitive element is an MOS type capacitive element which uses as both electrodes the n-type semiconductor region formed in the semiconductor substrate, and the upper electrode formed via the insulation film on the n-type semiconductor region. The MIM type capacitive element formed with the pattern of the comb-type of a wiring is arranged in the upper part of a lower capacitive element, and this is connected with a lower capacitive element in parallel.