Patents by Inventor Hidehiro Harata

Hidehiro Harata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220141411
    Abstract: To improve charge transfer efficiency in a solid-state imaging device that transfers a charge from a photoelectric conversion element to a floating diffusion layer. A solid-state imaging device is provided with a transfer transistor and a potential control unit. In this solid-state imaging device, the transfer transistor transfers a charge from a photoelectric conversion element to a floating diffusion layer in a predetermined transfer period according to a transfer signal transmitted through a predetermined transfer line. Furthermore, the potential control unit makes a potential in a transfer period of a predetermined signal line capacitively coupled with the floating diffusion layer higher than that outside the transfer period.
    Type: Application
    Filed: November 28, 2019
    Publication date: May 5, 2022
    Inventors: MAMORU SATO, AKIHIKO KATO, YUSUKE OIKE, HIDEHIRO HARATA, HIDEKI NAGANUMA
  • Publication number: 20080230820
    Abstract: Coexistence of the realization of high-capacity of a capacitive element and the area reduction of a semiconductor device is aimed at. A plurality of capacitive elements from which a kind differs mutually are accumulated and arranged on a semiconductor substrate, and they are connected in parallel. These capacitive elements are arranged to the same plane region, and make a plane size almost the same. A lower capacitive element is an MOS type capacitive element which uses as both electrodes the n-type semiconductor region formed in the semiconductor substrate, and the upper electrode formed via the insulation film on the n-type semiconductor region. The MIM type capacitive element formed with the pattern of the comb-type of a wiring is arranged in the upper part of a lower capacitive element, and this is connected with a lower capacitive element in parallel.
    Type: Application
    Filed: January 14, 2008
    Publication date: September 25, 2008
    Inventors: Satoshi Maeda, Hidehiro Harata, Hiroyuki Kono