Patents by Inventor Hidehiro Kanada

Hidehiro Kanada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090159309
    Abstract: A highly reliable flat cable is disclosed in which a short-circuit between adjacent electrodes due to whisker formation is prevented and the occurrence of contact failure between electrodes due to a foreign particle is prevented. A plasma display using this flat cable is also disclosed. The flat cable comprises a plurality of conductors and a pair of films having adhesive applied on the films so as to sandwich each of the conductors with a predetermined spacing. The conductors on the side of the flat cable or the conductors on the side of a connector electrically connected to the conductors on the side of the flat cable are formed of a lead-free material. Further, at a connecting portion of the flat cable, one of the films (2, 3) on which the adhesives (2a, 3a) are applied is removed to expose the conductors (1) to form electrodes (1a). A cover (11) is provided on the electrodes (1a) from which the film (2) has been removed.
    Type: Application
    Filed: August 22, 2005
    Publication date: June 25, 2009
    Inventors: Hidehiro Kanada, Nobuyoshi Kondo
  • Patent number: 4802192
    Abstract: An original code series containing a synchronizing code is divided into code series, n in number so as to reduce an operation rate to 1/n (n is a positive integer). The detection of a synchronizing pattern is conducted on the basis of a fact that an original synchronizing pattern is transformed into any of patterns of n kinds based on the phase of division.
    Type: Grant
    Filed: February 10, 1987
    Date of Patent: January 31, 1989
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Yoshizumi Eto, Kazuyuki Takeshita, Hidehiro Kanada, Masuo Umemoto
  • Patent number: 4791495
    Abstract: A digital recording and reproducing system wherein luminance signals digitized and converted into the low speed signals and chrominance signals digitized at the time of recording are distributed among a plural number of channels and the signals of the plural number of channels are recorded respectively on a recording medium. At the time of the reproduction, the signals of the plural number of the channels are reproduced respectively from the recording medium and combined to form the luminance signals and the chrominance signals respectively. The luminance signals in the combined signal are converted into a high speed signal and output terminals for outputting dubbing signals from the system for dubbing the signals are led. The output side of a low speed-to-high speed converter and a channel combination circuit.
    Type: Grant
    Filed: May 13, 1986
    Date of Patent: December 13, 1988
    Assignees: Hitachi Denshi Kabushiki Kaisha, Hitachi Ltd.
    Inventors: Masuo Umemoto, Yoshizumi Eto, Shinichi Miyazaki, Hidehiro Kanada, Hitoshi Katayama, Yuichi Michikawa
  • Patent number: 4775897
    Abstract: Disclosed is an apparatus in which a picture signal is converted into digital signals and the digital signals are recorded into a recording medium, and which is suitable to perform dubbing of the digital signals reproduced from the recording medium. The apparatus employs the component method in which a luminance signal and chrominance signals constituting a picture signal are recorded separately from each other. According to the component method, the sampling frequency of the chrominance signal is set to be about 1/3-1/4 of that of the luminance signal, and therefore the recording/reproducing of a picture signal is carried out after the bit rate of the digital luminance signal is converted into a value equal to the bit rate of the digital chrominance signal.
    Type: Grant
    Filed: May 27, 1986
    Date of Patent: October 4, 1988
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Masuo Umemoto, Yoshizumi Eto, Shinichi Miyazaki, Hidehiro Kanada, Hitoshi Katayama, Yuichi Michikawa
  • Patent number: 4700240
    Abstract: Number data affixed to individual digital data divided into a plurality of data blocks are sequentially read out from a recording medium to be used for determining the write-in positions of the digital data in a memory. For determining the write-in positions of the digital data, the number data of the next write-in position is estimated on the basis of the number data of the current write-in position. Judgment is made as to whether or not the number of times of continuous non-coincidence between the estimated number data and the successively read-out number data exceeds a predetermined setting, and, also judgment is made as to whether or not the number data read out each time falls within a predetermined range. Depending on the results of these judgments, one of the read-out number data and the estimated number data is selected to determine the next write-in position.
    Type: Grant
    Filed: November 5, 1985
    Date of Patent: October 13, 1987
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Masuo Umemoto, Yoshizumi Eto, Hidehiro Kanada, Morito Rokuda
  • Patent number: 4698811
    Abstract: An apparatus for recording or reproducing codes resulting from digitalizing a picture signal on or from a video tape recorder includes a device for correcting code error produced due to interference in the course of recording or reproducing process. The pixel codes succeeding to one another in time are divided to high-order and low-order bit-blocks, respectively, wherein the high-order bits are used to constitute a pseudo pixel code which is then added with a pixel error correcting code. The pixel code consisting of the high-order bits is added with a bit error correcting code before being recorded. In reproduction, error correction can be realized at higher rate with the aid of the correction codes to improve the quality of reproduced picture.
    Type: Grant
    Filed: July 19, 1985
    Date of Patent: October 6, 1987
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Yoshizumi Eto, Masuo Umemoto, Hidehiro Kanada, Seiichi Mita
  • Patent number: 4670797
    Abstract: An improved 8-8 mpping table system in digitally and magnetically recording video signals. Video signals coded into natural binary codes consisting of 8 bits are converted into different binary codes consisting of 8 bits constituted by patterns in which a continuous number of the 1's or the 0's does not exceed a predetermined number. In these codes, the continuous number of the 1's or the 0's is so limited that a maximum magnetization interval is reduced in magnetically recording the signals. Therefore, erroneous code is prevented from occurring in reproducing the signals.
    Type: Grant
    Filed: February 19, 1985
    Date of Patent: June 2, 1987
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Masuo Umenoto, Seiichi Mita, Morishi Izumita, Yuuichi Michikawa, Morito Rokuda, Hitoshi Katayama, Hidehiro Kanada
  • Patent number: 4661956
    Abstract: Parity bits (check bits) having a relatively high redundancy are added to upper significant bits of a digital signal, and parity bits having a relatively low redundancy, are added to the lower significant bits of the digital signal. The signal and the parity bits are recorded on a recording medium. The position of an error in a data block group of the lower bits reproduced from the recording medium is estimated as existing in a block in which the error is detected by the check of the data block group of the upper bits, and in the blocks preceding and subsequent to the former.This error correction method is most suitable for a recording and reproduction system of digital video signals.
    Type: Grant
    Filed: February 21, 1985
    Date of Patent: April 28, 1987
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Morishi Izumita, Seiichi Mita, Masuo Umemoto, Hidehiro Kanada, Morito Rokuda
  • Patent number: 4628297
    Abstract: In the code modulation system for converting input data levels into an output signal in the form of code words by providing M input levels among N input levels assigned to input data with stairlike code weights on the basis of the input levels, (N-M) input levels which are the difference between said N input levels and said M input levels are respectively disposed near transition points where said stairlike code weight is changed, and the code weights are provided with hysteresis in the ascent process and the descent process of the input data level.
    Type: Grant
    Filed: January 30, 1985
    Date of Patent: December 9, 1986
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Seiichi Mita, Morishi Izumita, Masuo Umemoto, Yoshizumi Eto, Morito Rokuda, Hidehiro Kanada