Patents by Inventor Hidehiro Nagaya

Hidehiro Nagaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7581137
    Abstract: A storage apparatus according to the present invention can store information related to a power supply abnormality after shutting down the principal functions of a data processing board when a power supply abnormality occurs in a data processing board. A power supply controller of a data processing board mounted in the storage apparatus monitors the operational status of DC/DC power supplies mounted to the data processing board, on the basis of detection signals from a voltage detection circuit. When a power supply abnormality is detected, the power supply controller immediately shuts down the operation of all the DC/DC power supplies. Shutting down the DC/DC power supplies also shuts down the principal functionality of the data processing board. Then, after storing information related to the power supply abnormality in memory, the power supply controller shuts down the auxiliary power supply.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: August 25, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Okada, Hidehiro Nagaya, Shin Nakamura
  • Patent number: 7409605
    Abstract: The failure management sections of a host computer and a storage unit are connected through a failure reporting interface. When a failure occurs in the storage unit, the failure information is notified from the failure management section of the storage unit to the failure management section of the host computer through the failure reporting interface, and the failure management section of the host computer deletes the failure information detected by software in the host computer based on the failure information from the storage unit. In this manner, the management of the failure information in the storage system can be unified by the service processor of the host computer. Consequently, it becomes possible to determine whether a failure generated in a host computer is a secondary failure or tertiary failure and to show the defect part indicating information minimum necessary for the maintenance and replacement.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: August 5, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Kato, Hidehiro Nagaya
  • Publication number: 20070260918
    Abstract: A storage apparatus according to the present invention can store information related to a power supply abnormality after shutting down the principal functions of a data processing board when a power supply abnormality occurs in a data processing board. A power supply controller of a data processing board mounted in the storage apparatus monitors the operational status of DC/DC power supplies mounted to the data processing board, on the basis of detection signals from a voltage detection circuit. When a power supply abnormality is detected, the power supply controller immediately shuts down the operation of all the DC/DC power supplies. Shutting down the DC/DC power supplies also shuts down the principal functionality of the data processing board. Then, after storing information related to the power supply abnormality in memory, the power supply controller shuts down the auxiliary power supply.
    Type: Application
    Filed: June 23, 2006
    Publication date: November 8, 2007
    Inventors: Naoki Okada, Hidehiro Nagaya, Shin Nakamura
  • Publication number: 20060184820
    Abstract: The failure management sections of a host computer and a storage unit are connected through a failure reporting interface. When a failure occurs in the storage unit, the failure information is notified from the failure management section of the storage unit to the failure management section of the host computer through the failure reporting interface, and the failure management section of the host computer deletes the failure information detected by software in the host computer based on the failure information from the storage unit. In this manner, the management of the failure information in the storage system can be unified by the service processor of the host computer. Consequently, it becomes possible to determine whether a failure generated in a host computer is a secondary failure or tertiary failure and to show the defect part indicating information minimum necessary for the maintenance and replacement.
    Type: Application
    Filed: April 26, 2005
    Publication date: August 17, 2006
    Inventors: Shinichi Kato, Hidehiro Nagaya
  • Patent number: 7073092
    Abstract: It is an object of the invention to provide a channel adapter and a disk array device that can retransmit partial data via an IP network and which are configured to be able to conduct a data guarantee of the partial data. CHA transmit data to host computers. The CHA compute an input guarantee code when the CHA store the data from a cache memory to a local memory. The CHA generate an output guarantee code when the CHA read the data from the local memory and transmit the data to a port unit. In a case where retransmission of partial data is requested after the transmission of the data, the CHA transmit the partial data to the host computers. Thereafter, the CHA again compute the output guarantee code of the data and compare it with the previously computed input guarantee code. In a case where both codes match, it is guaranteed that data transmission has been conducted normally.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: July 4, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Homare Okamoto, Hidehiro Nagaya
  • Publication number: 20050114574
    Abstract: It is an object of the invention to provide a channel adapter and a disk array device that can retransmit partial data via an IP network and which are configured to be able to conduct a data guarantee of the partial data. CHA transmit data to host computers. The CHA compute an input guarantee code when the CHA store the data from a cache memory to a local memory. The CHA generate an output guarantee code when the CHA read the data from the local memory and transmit the data to a port unit. In a case where retransmission of partial data is requested after the transmission of the data, the CHA transmit the partial data to the host computers. Thereafter, the CHA again compute the output guarantee code of the data and compare it with the previously computed input guarantee code. In a case where both codes match, it is guaranteed that data transmission has been conducted normally.
    Type: Application
    Filed: February 3, 2004
    Publication date: May 26, 2005
    Inventors: Homare Okamoto, Hidehiro Nagaya