Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.

Abstract: A semiconductor device includes a wiring substrate having an insulating film formed on a surface thereof, a first semiconductor chip mounted on the wiring substrate, and a second semiconductor chip stacked and mounted on the first semiconductor chip so as to form an overhang portion. The insulating film is removed from an area of the wiring substrate that faces the overhang portion.

Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.

Abstract: The present invention provides a semiconductor device which includes a semiconductor chip formed with an electrode pad on one surface thereof, a wiring board having a wiring pattern, with its one surface opposing the other surface of the semiconductor chip, a wire for electrically connecting the electrode pad of the semiconductor chip with the wiring pattern of the wiring board, an external terminal arranged on the other surface of the wiring board for electrical connection with the electrode pad through the wire and wiring pattern, and a sealant for fixing the semiconductor chip on one surface of the wiring board such that a hollow is formed between the other surface of the semiconductor chip and the one surface of the wiring board. The wiring board includes a throughhole communicating with the hollow.

Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.

Abstract: A method of analyzing thermal stress includes calculating a distribution of the number of fillers in a composite integrally molded product by using physical property values of resin material containing fillers, and determining a coefficient of linear expansion of the resin material in the composite integrally molded product, that is used as an input condition of a thermal stress analysis, based on the distribution of the number of the fillers.

Abstract: A semiconductor device includes a wiring substrate having an insulating film formed on a surface thereof, a first semiconductor chip mounted on the wiring substrate, and a second semiconductor chip stacked and mounted on the first semiconductor chip so as to form an overhang portion. The insulating film is removed from an area of the wiring substrate that faces the overhang portion.

Abstract: Semiconductor device 10 includes wiring substrate 11 including wiring 14 and wiring 15 in predetermined patterns, semiconductor chips 19 and 23 which are mounted on wiring substrate 11 with electrodes electrically connected to wiring 14 of wiring substrate 11 via wires 21 and 24, first sealing body 25 made of an insulative resin which is formed on a part of wiring substrate 11 and which covers semiconductor chips 19 and 23 and wires 21 and 24, a plurality of connecting connection pads 27 provided on the top surface of first sealing body 25, a plurality of connecting wires 26 which extend from the surface of wiring substrate 11, on which semiconductor chips 19 and 23 are mounted, to the top surface of first sealing body 25 via the side surfaces of first sealing body 25, and which electrically connect wiring 14 of wiring substrate 11 and the plurality of connecting connection pads 27 and second sealing body 28 made of an insulative resin which covers the plurality of connecting wires 26.

Abstract: A device has a semiconductor chip, a wiring board, a support which supports the semiconductor chip on the wiring board and forms a gap between the semiconductor chip and the wiring board, and a sealing resin injected into the gap and covering the semiconductor chip.

Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.

Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.

Abstract: The present invention provides a semiconductor device which includes a semiconductor chip formed with an electrode pad on one surface thereof, a wiring board having a wiring pattern, with its one surface opposing the other surface of the semiconductor chip, a wire for electrically connecting the electrode pad of the semiconductor chip with the wiring pattern of the wiring board, an external terminal arranged on the other surface of the wiring board for electrical connection with the electrode pad through the wire and wiring pattern, and a sealant for fixing the semiconductor chip on one surface of the wiring board such that a hollow is formed between the other surface of the semiconductor chip and the one surface of the wiring board. The wiring board includes a throughhole communicating with the hollow.

Abstract: A method of analyzing thermal stress includes calculating a distribution of the number of fillers in a composite integrally molded product by using physical property values of resin material containing fillers, and determining a coefficient of linear expansion of the resin material in the composite integrally molded product, that is used as an input condition of a thermal stress analysis, based on the distribution of the number of the fillers.

Abstract: Semiconductor device 10 includes wiring substrate 11 including wiring 14 and wiring 15 in predetermined patterns, semiconductor chips 19 and 23 which are mounted on wiring substrate 11 with electrodes electrically connected to wiring 14 of wiring substrate 11 via wires 21 and 24, first sealing body 25 made of an insulative resin which is formed on a part of wiring substrate 11 and which covers semiconductor chips 19 and 23 and wires 21 and 24, a plurality of connecting connection pads 27 provided on the top surface of first sealing body 25, a plurality of connecting wires 26 which extend from the surface of wiring substrate 11, on which semiconductor chips 19 and 23 are mounted, to the top surface of first sealing body 25 via the side surfaces of first sealing body 25, and which electrically connect wiring 14 of wiring substrate 11 and the plurality of connecting connection pads 27 and second sealing body 28 made of an insulative resin which covers the plurality of connecting wires 26.

Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.

Abstract: In a semiconductor device according to the present invention, a first bare chip, and a second bare chip having a wider principal surface than that of the first bare chip are connected to one principal surface and the other principal surface of an interposer substrate, respectively. In the semiconductor device, a resin having a larger coefficient of linear expansion than that of the second bare chip is applied to a backgrind surface (a principal surface at an opposite side to the interposer substrate) of the second bare chip, thereby preventing the second bare chip from cracking due to warpage of the interposer substrate.

Abstract: A non-leaded semiconductor device which does not cause a flaw and contamination with a foreign substance on mounting surfaces of external electrode terminals of another non-leaded semiconductor device, and a method of fabricating the same. In fabrication of the non-leaded semiconductor device, a matrix-type leadframe containing a matrix of a plurality of unit leadframe patterns is prepared, a semiconductor chip is secured on each unit leadframe pattern, conductive wires are connected between electrodes of the semiconductor chip and inner ends of terminal leads of each unit leadframe pattern, and then single-sided molding is performed to encapsulate the semiconductor chip, conductive wires, and inner end parts of terminal leads in a package part. In this single-sided molding, a contact-preventive part thicker than the package part is formed outside the package part using injected resin.

Abstract: A non-leaded semiconductor device which does not cause a flaw and contamination with a foreign substance on mounting surfaces of external electrode terminals of another non-leaded semiconductor device, and a method of fabricating the same. In fabrication of the non-leaded semiconductor device, a matrix-type leadframe containing a matrix of a plurality of unit leadframe patterns is prepared, a semiconductor chip is secured on each unit leadframe pattern, conductive wires are connected between electrodes of the semiconductor chip and inner ends of terminal leads of each unit leadframe pattern, and then single-sided molding is performed to encapsulate the semiconductor chip, conductive wires, and inner end parts of terminal leads in a package part. In this single-sided molding, a contact-preventive part thicker than the package part is formed outside the package part using injected resin.